Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	603990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

364667

1

T1

146

T2

1335

T3

152

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	516308	1			T1	186		T2	1989		T3	196
values[0x0]	225214	1			T1	96		T2	766		T3	92
values[0x1]	227135	1			T1	97		T2	825		T3	117

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	506988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

461669

1

T1

174

T2

1710

T3

189

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3241	1			T1	2		T2	10		T21	7
valid_sources[0x01]	3315	1			T1	2		T2	17		T6	1
valid_sources[0x02]	3946	1			T2	15		T4	2		T6	26
valid_sources[0x03]	3211	1			T1	1		T2	8		T6	9
valid_sources[0x04]	6834	1			T2	14		T4	2		T6	3
valid_sources[0x05]	2790	1			T2	8		T4	1		T9	2
valid_sources[0x06]	3689	1			T1	1		T2	18		T4	2
valid_sources[0x07]	3454	1			T1	1		T2	12		T4	1
valid_sources[0x08]	4030	1			T2	6		T6	1		T7	5
valid_sources[0x09]	3022	1			T1	3		T2	15		T6	5
valid_sources[0x0a]	3459	1			T2	11		T6	12		T7	2
valid_sources[0x0b]	3969	1			T2	22		T6	10		T7	2
valid_sources[0x0c]	3747	1			T2	19		T4	1		T6	4
valid_sources[0x0d]	3332	1			T1	1		T2	19		T10	1
valid_sources[0x0e]	4509	1			T2	12		T4	2		T6	23
valid_sources[0x0f]	3532	1			T2	12		T6	19		T10	3
valid_sources[0x10]	3206	1			T2	16		T6	3		T21	7
valid_sources[0x11]	3221	1			T1	2		T2	16		T4	2
valid_sources[0x12]	3750	1			T2	21		T4	1		T6	50
valid_sources[0x13]	3661	1			T2	12		T6	1		T21	8
valid_sources[0x14]	4278	1			T2	9		T6	8		T7	1
valid_sources[0x15]	3311	1			T1	3		T2	10		T10	2
valid_sources[0x16]	3908	1			T2	18		T4	3		T6	33
valid_sources[0x17]	2960	1			T1	2		T2	21		T6	2
valid_sources[0x18]	3954	1			T2	10		T6	4		T21	10
valid_sources[0x19]	3513	1			T2	13		T4	3		T6	14
valid_sources[0x1a]	3598	1			T2	12		T4	2		T7	2
valid_sources[0x1b]	3736	1			T2	11		T21	9		T57	33
valid_sources[0x1c]	3575	1			T2	12		T4	2		T6	6
valid_sources[0x1d]	3771	1			T2	14		T4	1		T6	9
valid_sources[0x1e]	3723	1			T2	12		T4	1		T6	1
valid_sources[0x1f]	3177	1			T1	1		T2	14		T10	3
valid_sources[0x20]	3479	1			T1	8		T2	14		T6	1
valid_sources[0x21]	3050	1			T1	1		T2	17		T4	1
valid_sources[0x22]	4547	1			T1	2		T2	12		T4	1
valid_sources[0x23]	5654	1			T2	18		T4	3		T6	6
valid_sources[0x24]	3396	1			T2	17		T6	2		T21	10
valid_sources[0x25]	3761	1			T2	15		T6	20		T7	1
valid_sources[0x26]	3434	1			T1	6		T2	12		T6	7
valid_sources[0x27]	3323	1			T2	12		T4	2		T6	7
valid_sources[0x28]	3984	1			T1	4		T2	12		T6	29
valid_sources[0x29]	3318	1			T2	13		T4	3		T6	4
valid_sources[0x2a]	3710	1			T2	17		T4	4		T6	2
valid_sources[0x2b]	3301	1			T2	13		T4	1		T6	3
valid_sources[0x2c]	3293	1			T1	2		T2	15		T4	2
valid_sources[0x2d]	6420	1			T2	22		T4	2		T7	4
valid_sources[0x2e]	3991	1			T1	2		T2	8		T4	1
valid_sources[0x2f]	3071	1			T2	17		T7	2		T21	8
valid_sources[0x30]	3618	1			T1	1		T2	18		T21	7
valid_sources[0x31]	3244	1			T1	2		T2	11		T4	1
valid_sources[0x32]	3193	1			T1	1		T2	22		T4	3
valid_sources[0x33]	3192	1			T1	1		T2	7		T4	1
valid_sources[0x34]	3712	1			T2	16		T4	1		T6	6
valid_sources[0x35]	3635	1			T2	23		T4	2		T6	5
valid_sources[0x36]	3133	1			T1	6		T2	19		T4	1
valid_sources[0x37]	3706	1			T1	6		T2	18		T4	2
valid_sources[0x38]	4016	1			T1	1		T2	11		T6	5
valid_sources[0x39]	3224	1			T2	20		T4	1		T6	38
valid_sources[0x3a]	3824	1			T1	3		T2	12		T6	14
valid_sources[0x3b]	3993	1			T1	5		T2	18		T6	21
valid_sources[0x3c]	4479	1			T1	2		T2	20		T21	15
valid_sources[0x3d]	3262	1			T1	3		T2	16		T6	11
valid_sources[0x3e]	3659	1			T1	5		T2	20		T4	2
valid_sources[0x3f]	2950	1			T2	20		T21	11		T69	2
valid_sources[0x40]	4839	1			T1	2		T2	22		T4	1
valid_sources[0x41]	3786	1			T2	16		T4	4		T6	13
valid_sources[0x42]	3869	1			T1	4		T2	15		T3	405
valid_sources[0x43]	3643	1			T2	14		T6	9		T21	15
valid_sources[0x44]	4283	1			T1	3		T2	7		T6	6
valid_sources[0x45]	3646	1			T2	10		T4	2		T6	5
valid_sources[0x46]	3634	1			T1	3		T2	12		T4	2
valid_sources[0x47]	3660	1			T2	15		T4	2		T7	2
valid_sources[0x48]	3636	1			T1	1		T2	15		T4	2
valid_sources[0x49]	4101	1			T2	15		T6	2		T21	18
valid_sources[0x4a]	3790	1			T2	19		T6	8		T10	2
valid_sources[0x4b]	3502	1			T2	12		T4	1		T6	7
valid_sources[0x4c]	2905	1			T1	4		T2	8		T6	4
valid_sources[0x4d]	3478	1			T1	1		T2	17		T4	1
valid_sources[0x4e]	3515	1			T2	18		T4	4		T10	1
valid_sources[0x4f]	3584	1			T1	6		T2	17		T4	2
valid_sources[0x50]	3997	1			T1	6		T2	17		T6	38
valid_sources[0x51]	3242	1			T1	1		T2	19		T6	7
valid_sources[0x52]	7958	1			T2	15		T4	1		T21	7
valid_sources[0x53]	3474	1			T2	10		T4	3		T21	25
valid_sources[0x54]	3102	1			T2	13		T4	2		T6	34
valid_sources[0x55]	4317	1			T1	1		T2	14		T4	1
valid_sources[0x56]	3733	1			T2	11		T4	1		T6	14
valid_sources[0x57]	3878	1			T2	9		T4	4		T10	1
valid_sources[0x58]	3235	1			T1	3		T2	9		T6	10
valid_sources[0x59]	3117	1			T2	8		T6	19		T10	2
valid_sources[0x5a]	3086	1			T1	3		T2	10		T4	2
valid_sources[0x5b]	3355	1			T1	1		T2	13		T6	19
valid_sources[0x5c]	3110	1			T2	10		T6	7		T7	1
valid_sources[0x5d]	3917	1			T1	5		T2	19		T4	4
valid_sources[0x5e]	3847	1			T2	17		T6	2		T21	7
valid_sources[0x5f]	3688	1			T2	12		T6	5		T7	4
valid_sources[0x60]	3562	1			T2	14		T10	1		T21	8
valid_sources[0x61]	3325	1			T1	2		T2	16		T7	3
valid_sources[0x62]	3616	1			T1	4		T2	12		T6	26
valid_sources[0x63]	4646	1			T2	14		T4	1		T10	1
valid_sources[0x64]	3469	1			T1	2		T2	12		T6	33
valid_sources[0x65]	4136	1			T1	1		T2	11		T4	3
valid_sources[0x66]	6750	1			T2	22		T6	4		T7	1
valid_sources[0x67]	4610	1			T1	5		T2	11		T6	13
valid_sources[0x68]	3662	1			T2	26		T4	3		T6	4
valid_sources[0x69]	3699	1			T2	6		T6	1		T10	2
valid_sources[0x6a]	4695	1			T1	1		T2	13		T6	47
valid_sources[0x6b]	3183	1			T1	3		T2	15		T4	4
valid_sources[0x6c]	3120	1			T1	1		T2	20		T6	17
valid_sources[0x6d]	3489	1			T2	14		T4	6		T6	18
valid_sources[0x6e]	3317	1			T2	8		T4	3		T6	5
valid_sources[0x6f]	3743	1			T1	2		T2	15		T6	8
valid_sources[0x70]	3054	1			T2	12		T6	27		T7	1
valid_sources[0x71]	4463	1			T2	14		T4	2		T7	4
valid_sources[0x72]	4559	1			T1	2		T2	11		T6	19
valid_sources[0x73]	2977	1			T1	3		T2	9		T4	1
valid_sources[0x74]	3384	1			T1	3		T2	14		T4	3
valid_sources[0x75]	3576	1			T1	1		T2	14		T21	12
valid_sources[0x76]	3947	1			T1	3		T2	13		T4	3
valid_sources[0x77]	3309	1			T2	23		T6	1		T7	5
valid_sources[0x78]	3144	1			T2	13		T6	9		T7	1
valid_sources[0x79]	3100	1			T2	9		T4	2		T6	4
valid_sources[0x7a]	3865	1			T1	7		T2	8		T7	5
valid_sources[0x7b]	3484	1			T1	1		T2	23		T6	6
valid_sources[0x7c]	3368	1			T1	3		T2	11		T4	1
valid_sources[0x7d]	4045	1			T1	7		T2	8		T4	2
valid_sources[0x7e]	3443	1			T2	15		T4	6		T6	7
valid_sources[0x7f]	4199	1			T1	5		T2	9		T4	1
valid_sources[0x80]	4072	1			T1	3		T2	22		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243252

1

T1

91

T2

926

T3

99

values[0x0]

all_enables

biggest_size

78828

1

T1

40

T2

254

T3

30

values[0x1]

all_enables

biggest_size

42587

1

T1

15

T2

155

T3

23