Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T57
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T57
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T57
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T57,T71
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T57,T70
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T57,T71
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12398970	13626	0	0
gen_assertions[0].RstEnOn_A	12398970	1100	0	0
gen_assertions[0].RstNOff_A	12398970	13626	0	0
gen_assertions[0].RstNOn_A	12398970	1100	0	0
gen_assertions[1].RstEnOff_A	49595788	12432	0	0
gen_assertions[1].RstEnOn_A	49595788	1067	0	0
gen_assertions[1].RstNOff_A	49595788	12432	0	0
gen_assertions[1].RstNOn_A	49595788	1067	0	0
gen_assertions[2].RstEnOff_A	24798858	12455	0	0
gen_assertions[2].RstEnOn_A	24798858	1040	0	0
gen_assertions[2].RstNOff_A	24798858	12455	0	0
gen_assertions[2].RstNOn_A	24798858	1040	0	0
gen_assertions[3].RstEnOff_A	24798782	12508	0	0
gen_assertions[3].RstEnOn_A	24798782	1086	0	0
gen_assertions[3].RstNOff_A	24798782	12508	0	0
gen_assertions[3].RstNOn_A	24798782	1086	0	0
gen_assertions[4].RstEnOff_A	1565791	20680	0	0
gen_assertions[4].RstEnOn_A	1565791	1136	0	0
gen_assertions[4].RstNOff_A	1565791	20680	0	0
gen_assertions[4].RstNOn_A	1565791	1136	0	0
gen_assertions[5].RstEnOff_A	12398970	13843	0	0
gen_assertions[5].RstEnOn_A	12398970	1162	0	0
gen_assertions[5].RstNOff_A	12398970	13843	0	0
gen_assertions[5].RstNOn_A	12398970	1162	0	0
gen_assertions[6].RstEnOff_A	12398970	13928	0	0
gen_assertions[6].RstEnOn_A	12398970	1238	0	0
gen_assertions[6].RstNOff_A	12398970	13928	0	0
gen_assertions[6].RstNOn_A	12398970	1238	0	0
gen_assertions[7].RstEnOff_A	12398970	13966	0	0
gen_assertions[7].RstEnOn_A	12398970	1275	0	0
gen_assertions[7].RstNOff_A	12398970	13966	0	0
gen_assertions[7].RstNOn_A	12398970	1275	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13626	0	0
T1	4962	4	0	0
T2	58670	45	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1100	0	0
T2	58670	9	0	0
T3	4117	10	0	0
T4	3174	6	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	4	0	0
T11	3547	0	0	0
T57	0	14	0	0
T69	0	1	0	0
T71	0	7	0	0
T94	0	7	0	0
T95	0	3	0	0
T96	0	36	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13626	0	0
T1	4962	4	0	0
T2	58670	45	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1100	0	0
T2	58670	9	0	0
T3	4117	10	0	0
T4	3174	6	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	4	0	0
T11	3547	0	0	0
T57	0	14	0	0
T69	0	1	0	0
T71	0	7	0	0
T94	0	7	0	0
T95	0	3	0	0
T96	0	36	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49595788	12432	0	0
T1	19852	4	0	0
T2	234679	43	0	0
T3	16474	18	0	0
T4	12699	13	0	0
T5	19422	0	0	0
T6	172816	29	0	0
T7	14183	4	0	0
T8	82303	28	0	0
T9	6765	0	0	0
T10	23564	15	0	0
T11	0	4	0	0
T21	0	38	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49595788	1067	0	0
T2	234679	10	0	0
T3	16474	8	0	0
T4	12699	5	0	0
T5	19422	0	0	0
T6	172816	0	0	0
T7	14183	0	0	0
T8	82303	0	0	0
T9	6765	0	0	0
T10	23564	0	0	0
T11	14187	0	0	0
T49	0	4	0	0
T57	0	15	0	0
T71	0	6	0	0
T72	0	2	0	0
T94	0	2	0	0
T96	0	34	0	0
T97	0	11	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49595788	12432	0	0
T1	19852	4	0	0
T2	234679	43	0	0
T3	16474	18	0	0
T4	12699	13	0	0
T5	19422	0	0	0
T6	172816	29	0	0
T7	14183	4	0	0
T8	82303	28	0	0
T9	6765	0	0	0
T10	23564	15	0	0
T11	0	4	0	0
T21	0	38	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49595788	1067	0	0
T2	234679	10	0	0
T3	16474	8	0	0
T4	12699	5	0	0
T5	19422	0	0	0
T6	172816	0	0	0
T7	14183	0	0	0
T8	82303	0	0	0
T9	6765	0	0	0
T10	23564	0	0	0
T11	14187	0	0	0
T49	0	4	0	0
T57	0	15	0	0
T71	0	6	0	0
T72	0	2	0	0
T94	0	2	0	0
T96	0	34	0	0
T97	0	11	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798858	12455	0	0
T1	9924	4	0	0
T2	117357	42	0	0
T3	8237	18	0	0
T4	6349	13	0	0
T5	9710	0	0	0
T6	86408	29	0	0
T7	7094	4	0	0
T8	41140	28	0	0
T9	3382	0	0	0
T10	11782	15	0	0
T11	0	4	0	0
T21	0	38	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798858	1040	0	0
T2	117357	8	0	0
T3	8237	0	0	0
T4	6349	1	0	0
T5	9710	0	0	0
T6	86408	0	0	0
T7	7094	0	0	0
T8	41140	0	0	0
T9	3382	0	0	0
T10	11782	0	0	0
T11	7093	0	0	0
T49	0	5	0	0
T50	0	5	0	0
T51	0	5	0	0
T57	0	18	0	0
T71	0	9	0	0
T72	0	3	0	0
T96	0	34	0	0
T97	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798858	12455	0	0
T1	9924	4	0	0
T2	117357	42	0	0
T3	8237	18	0	0
T4	6349	13	0	0
T5	9710	0	0	0
T6	86408	29	0	0
T7	7094	4	0	0
T8	41140	28	0	0
T9	3382	0	0	0
T10	11782	15	0	0
T11	0	4	0	0
T21	0	38	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798858	1040	0	0
T2	117357	8	0	0
T3	8237	0	0	0
T4	6349	1	0	0
T5	9710	0	0	0
T6	86408	0	0	0
T7	7094	0	0	0
T8	41140	0	0	0
T9	3382	0	0	0
T10	11782	0	0	0
T11	7093	0	0	0
T49	0	5	0	0
T50	0	5	0	0
T51	0	5	0	0
T57	0	18	0	0
T71	0	9	0	0
T72	0	3	0	0
T96	0	34	0	0
T97	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798782	12508	0	0
T1	9926	5	0	0
T2	117347	43	0	0
T3	8236	18	0	0
T4	6349	13	0	0
T5	9710	0	0	0
T6	86418	29	0	0
T7	7093	4	0	0
T8	41136	28	0	0
T9	3381	0	0	0
T10	11782	15	0	0
T11	0	4	0	0
T21	0	38	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798782	1086	0	0
T1	9926	1	0	0
T2	117347	10	0	0
T3	8236	0	0	0
T4	6349	0	0	0
T5	9710	0	0	0
T6	86418	0	0	0
T7	7093	0	0	0
T8	41136	0	0	0
T9	3381	0	0	0
T10	11782	0	0	0
T49	0	6	0	0
T50	0	6	0	0
T51	0	6	0	0
T57	0	16	0	0
T71	0	11	0	0
T72	0	4	0	0
T96	0	34	0	0
T97	0	13	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798782	12508	0	0
T1	9926	5	0	0
T2	117347	43	0	0
T3	8236	18	0	0
T4	6349	13	0	0
T5	9710	0	0	0
T6	86418	29	0	0
T7	7093	4	0	0
T8	41136	28	0	0
T9	3381	0	0	0
T10	11782	15	0	0
T11	0	4	0	0
T21	0	38	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798782	1086	0	0
T1	9926	1	0	0
T2	117347	10	0	0
T3	8236	0	0	0
T4	6349	0	0	0
T5	9710	0	0	0
T6	86418	0	0	0
T7	7093	0	0	0
T8	41136	0	0	0
T9	3381	0	0	0
T10	11782	0	0	0
T49	0	6	0	0
T50	0	6	0	0
T51	0	6	0	0
T57	0	16	0	0
T71	0	11	0	0
T72	0	4	0	0
T96	0	34	0	0
T97	0	13	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	20680	0	0
T1	618	7	0	0
T2	7403	69	0	0
T3	513	19	0	0
T4	395	14	0	0
T5	606	2	0	0
T6	5464	55	0	0
T7	441	6	0	0
T8	2632	52	0	0
T9	211	1	0	0
T10	734	17	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	1136	0	0
T1	618	1	0	0
T2	7403	7	0	0
T3	513	0	0	0
T4	395	0	0	0
T5	606	0	0	0
T6	5464	0	0	0
T7	441	0	0	0
T8	2632	0	0	0
T9	211	0	0	0
T10	734	0	0	0
T49	0	7	0	0
T50	0	5	0	0
T51	0	6	0	0
T57	0	18	0	0
T71	0	9	0	0
T72	0	5	0	0
T96	0	38	0	0
T97	0	10	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	20680	0	0
T1	618	7	0	0
T2	7403	69	0	0
T3	513	19	0	0
T4	395	14	0	0
T5	606	2	0	0
T6	5464	55	0	0
T7	441	6	0	0
T8	2632	52	0	0
T9	211	1	0	0
T10	734	17	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	1136	0	0
T1	618	1	0	0
T2	7403	7	0	0
T3	513	0	0	0
T4	395	0	0	0
T5	606	0	0	0
T6	5464	0	0	0
T7	441	0	0	0
T8	2632	0	0	0
T9	211	0	0	0
T10	734	0	0	0
T49	0	7	0	0
T50	0	5	0	0
T51	0	6	0	0
T57	0	18	0	0
T71	0	9	0	0
T72	0	5	0	0
T96	0	38	0	0
T97	0	10	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13843	0	0
T1	4962	4	0	0
T2	58670	46	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1162	0	0
T2	58670	11	0	0
T3	4117	0	0	0
T4	3174	0	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	0	0	0
T11	3547	0	0	0
T49	0	7	0	0
T50	0	5	0	0
T51	0	6	0	0
T57	0	18	0	0
T71	0	10	0	0
T72	0	6	0	0
T96	0	36	0	0
T97	0	7	0	0
T98	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13843	0	0
T1	4962	4	0	0
T2	58670	46	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1162	0	0
T2	58670	11	0	0
T3	4117	0	0	0
T4	3174	0	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	0	0	0
T11	3547	0	0	0
T49	0	7	0	0
T50	0	5	0	0
T51	0	6	0	0
T57	0	18	0	0
T71	0	10	0	0
T72	0	6	0	0
T96	0	36	0	0
T97	0	7	0	0
T98	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13928	0	0
T1	4962	4	0	0
T2	58670	46	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1238	0	0
T2	58670	11	0	0
T3	4117	0	0	0
T4	3174	0	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	0	0	0
T11	3547	0	0	0
T49	0	9	0	0
T50	0	6	0	0
T51	0	9	0	0
T57	0	13	0	0
T70	0	1	0	0
T71	0	13	0	0
T72	0	7	0	0
T96	0	34	0	0
T97	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13928	0	0
T1	4962	4	0	0
T2	58670	46	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1238	0	0
T2	58670	11	0	0
T3	4117	0	0	0
T4	3174	0	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	0	0	0
T11	3547	0	0	0
T49	0	9	0	0
T50	0	6	0	0
T51	0	9	0	0
T57	0	13	0	0
T70	0	1	0	0
T71	0	13	0	0
T72	0	7	0	0
T96	0	34	0	0
T97	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13966	0	0
T1	4962	4	0	0
T2	58670	46	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1275	0	0
T2	58670	11	0	0
T3	4117	0	0	0
T4	3174	0	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	0	0	0
T11	3547	0	0	0
T49	0	8	0	0
T50	0	8	0	0
T51	0	9	0	0
T57	0	14	0	0
T71	0	13	0	0
T72	0	8	0	0
T96	0	37	0	0
T97	0	8	0	0
T98	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	13966	0	0
T1	4962	4	0	0
T2	58670	46	0	0
T3	4117	20	0	0
T4	3174	13	0	0
T5	4855	0	0	0
T6	43217	32	0	0
T7	3546	4	0	0
T8	20569	32	0	0
T9	1690	0	0	0
T10	5890	16	0	0
T11	0	4	0	0
T21	0	41	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	1275	0	0
T2	58670	11	0	0
T3	4117	0	0	0
T4	3174	0	0	0
T5	4855	0	0	0
T6	43217	0	0	0
T7	3546	0	0	0
T8	20569	0	0	0
T9	1690	0	0	0
T10	5890	0	0	0
T11	3547	0	0	0
T49	0	8	0	0
T50	0	8	0	0
T51	0	9	0	0
T57	0	14	0	0
T71	0	13	0	0
T72	0	8	0	0
T96	0	37	0	0
T97	0	8	0	0
T98	0	1	0	0