Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11814974	8462	0	0
alert_regwen_rd_A	11814974	5670	0	0
cpu_regwen_rd_A	11814974	5544	0	0
sw_rst_ctrl_n_0_rd_A	11814974	11483	0	0
sw_rst_ctrl_n_1_rd_A	11814974	11712	0	0
sw_rst_ctrl_n_2_rd_A	11814974	11724	0	0
sw_rst_ctrl_n_3_rd_A	11814974	11403	0	0
sw_rst_ctrl_n_4_rd_A	11814974	11651	0	0
sw_rst_ctrl_n_5_rd_A	11814974	11536	0	0
sw_rst_ctrl_n_6_rd_A	11814974	11858	0	0
sw_rst_ctrl_n_7_rd_A	11814974	11779	0	0
sw_rst_regwen_0_rd_A	11814974	6176	0	0
sw_rst_regwen_1_rd_A	11814974	6091	0	0
sw_rst_regwen_2_rd_A	11814974	6331	0	0
sw_rst_regwen_3_rd_A	11814974	6277	0	0
sw_rst_regwen_4_rd_A	11814974	6416	0	0
sw_rst_regwen_5_rd_A	11814974	6123	0	0
sw_rst_regwen_6_rd_A	11814974	5991	0	0
sw_rst_regwen_7_rd_A	11814974	6385	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	8462	0	0
T74	4656	14	0	0
T75	2578	2	0	0
T77	4068	509	0	0
T78	2496	278	0	0
T79	4985	605	0	0
T88	3556	27	0	0
T99	4128	41	0	0
T100	4056	18	0	0
T101	4717	18	0	0
T115	17634	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	5670	0	0
T2	53730	85	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	94	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	56	0	0
T38	0	26	0	0
T103	0	78	0	0
T106	0	428	0	0
T126	0	587	0	0
T127	0	477	0	0
T128	0	80	0	0
T129	0	56	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	5544	0	0
T2	53730	74	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	42	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	39	0	0
T38	0	42	0	0
T103	0	84	0	0
T106	0	439	0	0
T126	0	621	0	0
T127	0	474	0	0
T128	0	82	0	0
T129	0	50	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11483	0	0
T2	53730	174	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	40	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	50	0	0
T11	3354	0	0	0
T46	0	59	0	0
T49	0	145	0	0
T71	0	160	0	0
T72	0	100	0	0
T103	0	106	0	0
T130	0	23	0	0
T131	0	6	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11712	0	0
T2	53730	213	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	47	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	71	0	0
T11	3354	0	0	0
T46	0	82	0	0
T49	0	127	0	0
T71	0	215	0	0
T72	0	56	0	0
T103	0	94	0	0
T130	0	9	0	0
T131	0	8	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11724	0	0
T2	53730	194	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	47	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	53	0	0
T11	3354	0	0	0
T46	0	54	0	0
T49	0	148	0	0
T71	0	180	0	0
T72	0	83	0	0
T103	0	68	0	0
T130	0	15	0	0
T131	0	6	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11403	0	0
T2	53730	204	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	38	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	43	0	0
T11	3354	0	0	0
T46	0	61	0	0
T49	0	153	0	0
T71	0	191	0	0
T72	0	46	0	0
T103	0	84	0	0
T130	0	14	0	0
T131	0	7	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11651	0	0
T2	53730	243	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	41	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	42	0	0
T11	3354	0	0	0
T46	0	55	0	0
T49	0	157	0	0
T71	0	165	0	0
T72	0	88	0	0
T103	0	72	0	0
T130	0	21	0	0
T131	0	11	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11536	0	0
T2	53730	195	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	52	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	65	0	0
T11	3354	0	0	0
T46	0	53	0	0
T49	0	152	0	0
T71	0	186	0	0
T72	0	88	0	0
T103	0	80	0	0
T130	0	8	0	0
T131	0	5	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11858	0	0
T2	53730	241	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	62	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	61	0	0
T11	3354	0	0	0
T46	0	68	0	0
T49	0	136	0	0
T71	0	203	0	0
T72	0	71	0	0
T103	0	81	0	0
T130	0	18	0	0
T131	0	11	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	11779	0	0
T2	53730	230	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	57	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	69	0	0
T11	3354	0	0	0
T46	0	52	0	0
T49	0	173	0	0
T71	0	197	0	0
T72	0	74	0	0
T103	0	74	0	0
T130	0	16	0	0
T131	0	4	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6176	0	0
T2	53730	72	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	27	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	38	0	0
T38	0	56	0	0
T49	0	19	0	0
T71	0	29	0	0
T72	0	14	0	0
T103	0	96	0	0
T106	0	472	0	0
T130	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6091	0	0
T2	53730	92	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	29	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	63	0	0
T38	0	37	0	0
T49	0	29	0	0
T71	0	28	0	0
T72	0	4	0	0
T103	0	72	0	0
T106	0	472	0	0
T130	0	3	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6331	0	0
T2	53730	55	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	26	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	54	0	0
T38	0	39	0	0
T49	0	22	0	0
T71	0	26	0	0
T72	0	26	0	0
T103	0	88	0	0
T106	0	478	0	0
T130	0	11	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6277	0	0
T2	53730	62	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	54	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	46	0	0
T38	0	50	0	0
T49	0	29	0	0
T71	0	22	0	0
T72	0	3	0	0
T103	0	100	0	0
T106	0	437	0	0
T132	0	6	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6416	0	0
T2	53730	73	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	54	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	45	0	0
T38	0	46	0	0
T49	0	17	0	0
T71	0	19	0	0
T72	0	19	0	0
T103	0	96	0	0
T106	0	448	0	0
T130	0	1	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6123	0	0
T2	53730	82	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	31	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	51	0	0
T38	0	37	0	0
T49	0	24	0	0
T71	0	34	0	0
T72	0	24	0	0
T103	0	83	0	0
T106	0	446	0	0
T130	0	4	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	5991	0	0
T2	53730	82	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	35	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	45	0	0
T38	0	44	0	0
T49	0	19	0	0
T71	0	27	0	0
T72	0	7	0	0
T103	0	92	0	0
T106	0	502	0	0
T130	0	3	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11814974	6385	0	0
T2	53730	83	0	0
T3	2849	0	0	0
T4	2247	0	0	0
T5	4692	0	0	0
T6	38026	33	0	0
T7	3260	0	0	0
T8	16070	0	0	0
T9	1672	0	0	0
T10	4949	0	0	0
T11	3354	0	0	0
T37	0	61	0	0
T38	0	44	0	0
T49	0	43	0	0
T71	0	20	0	0
T72	0	11	0	0
T103	0	70	0	0
T106	0	429	0	0
T130	0	3	0	0