Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T6,T8

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51664008	8231	0	0
CascadeEffAonToRstPorAboveRise_A	51664008	8231	0	0
CascadeEffAonToRstPorIoAboveFall_A	49595788	8231	0	0
CascadeEffAonToRstPorIoAboveRise_A	49595788	8231	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24798858	8231	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24798858	8231	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12398970	8231	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12398970	8231	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24798782	8231	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24798782	8231	0	0
CascadeLcToLcAboveFall_A	51664008	20949	0	0
CascadeLcToLcAboveRise_A	51664008	20949	0	0
CascadeLcToLcAonAboveFall_A	1565791	20949	0	0
CascadeLcToLcAonAboveRise_A	1565791	20949	0	0
CascadeLcToLcShadowedAboveFall_A	51664008	20949	0	0
CascadeLcToLcShadowedAboveRise_A	51664008	20949	0	0
CascadePorToAonAboveFall_A	1565791	6566	0	0
CascadeSysToSysAboveFall_A	51664008	20949	0	0
CascadeSysToSysAboveRise_A	51664008	20949	0	0
ScanRstToAonRise_A	1565791	203	0	0
StablePorToAonRise_A	1565791	8231	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10985737	20949	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10985737	20949	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10985737	20949	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10985737	20949	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12398970	20949	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12398970	20949	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10985737	20949	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10985737	20949	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10985737	20949	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10985737	20949	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	8231	0	0
T1	20678	2	0	0
T2	244474	26	0	0
T3	17159	1	0	0
T4	13228	1	0	0
T5	20231	2	0	0
T6	180038	23	0	0
T7	14779	2	0	0
T8	85730	20	0	0
T9	7047	1	0	0
T10	24547	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	8231	0	0
T1	20678	2	0	0
T2	244474	26	0	0
T3	17159	1	0	0
T4	13228	1	0	0
T5	20231	2	0	0
T6	180038	23	0	0
T7	14779	2	0	0
T8	85730	20	0	0
T9	7047	1	0	0
T10	24547	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49595788	8231	0	0
T1	19852	2	0	0
T2	234679	26	0	0
T3	16474	1	0	0
T4	12699	1	0	0
T5	19422	2	0	0
T6	172816	23	0	0
T7	14183	2	0	0
T8	82303	20	0	0
T9	6765	1	0	0
T10	23564	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49595788	8231	0	0
T1	19852	2	0	0
T2	234679	26	0	0
T3	16474	1	0	0
T4	12699	1	0	0
T5	19422	2	0	0
T6	172816	23	0	0
T7	14183	2	0	0
T8	82303	20	0	0
T9	6765	1	0	0
T10	23564	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798858	8231	0	0
T1	9924	2	0	0
T2	117357	26	0	0
T3	8237	1	0	0
T4	6349	1	0	0
T5	9710	2	0	0
T6	86408	23	0	0
T7	7094	2	0	0
T8	41140	20	0	0
T9	3382	1	0	0
T10	11782	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798858	8231	0	0
T1	9924	2	0	0
T2	117357	26	0	0
T3	8237	1	0	0
T4	6349	1	0	0
T5	9710	2	0	0
T6	86408	23	0	0
T7	7094	2	0	0
T8	41140	20	0	0
T9	3382	1	0	0
T10	11782	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	8231	0	0
T1	4962	2	0	0
T2	58670	26	0	0
T3	4117	1	0	0
T4	3174	1	0	0
T5	4855	2	0	0
T6	43217	23	0	0
T7	3546	2	0	0
T8	20569	20	0	0
T9	1690	1	0	0
T10	5890	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	8231	0	0
T1	4962	2	0	0
T2	58670	26	0	0
T3	4117	1	0	0
T4	3174	1	0	0
T5	4855	2	0	0
T6	43217	23	0	0
T7	3546	2	0	0
T8	20569	20	0	0
T9	1690	1	0	0
T10	5890	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798782	8231	0	0
T1	9926	2	0	0
T2	117347	26	0	0
T3	8236	1	0	0
T4	6349	1	0	0
T5	9710	2	0	0
T6	86418	23	0	0
T7	7093	2	0	0
T8	41136	20	0	0
T9	3381	1	0	0
T10	11782	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24798782	8231	0	0
T1	9926	2	0	0
T2	117347	26	0	0
T3	8236	1	0	0
T4	6349	1	0	0
T5	9710	2	0	0
T6	86418	23	0	0
T7	7093	2	0	0
T8	41136	20	0	0
T9	3381	1	0	0
T10	11782	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	20949	0	0
T1	20678	6	0	0
T2	244474	62	0	0
T3	17159	21	0	0
T4	13228	14	0	0
T5	20231	2	0	0
T6	180038	55	0	0
T7	14779	6	0	0
T8	85730	52	0	0
T9	7047	1	0	0
T10	24547	17	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	20949	0	0
T1	20678	6	0	0
T2	244474	62	0	0
T3	17159	21	0	0
T4	13228	14	0	0
T5	20231	2	0	0
T6	180038	55	0	0
T7	14779	6	0	0
T8	85730	52	0	0
T9	7047	1	0	0
T10	24547	17	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	20949	0	0
T1	618	6	0	0
T2	7403	62	0	0
T3	513	21	0	0
T4	395	14	0	0
T5	606	2	0	0
T6	5464	55	0	0
T7	441	6	0	0
T8	2632	52	0	0
T9	211	1	0	0
T10	734	17	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	20949	0	0
T1	618	6	0	0
T2	7403	62	0	0
T3	513	21	0	0
T4	395	14	0	0
T5	606	2	0	0
T6	5464	55	0	0
T7	441	6	0	0
T8	2632	52	0	0
T9	211	1	0	0
T10	734	17	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	20949	0	0
T1	20678	6	0	0
T2	244474	62	0	0
T3	17159	21	0	0
T4	13228	14	0	0
T5	20231	2	0	0
T6	180038	55	0	0
T7	14779	6	0	0
T8	85730	52	0	0
T9	7047	1	0	0
T10	24547	17	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	20949	0	0
T1	20678	6	0	0
T2	244474	62	0	0
T3	17159	21	0	0
T4	13228	14	0	0
T5	20231	2	0	0
T6	180038	55	0	0
T7	14779	6	0	0
T8	85730	52	0	0
T9	7047	1	0	0
T10	24547	17	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	6566	0	0
T1	618	1	0	0
T2	7403	12	0	0
T3	513	1	0	0
T4	395	1	0	0
T5	606	18	0	0
T6	5464	15	0	0
T7	441	1	0	0
T8	2632	8	0	0
T9	211	1	0	0
T10	734	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	20949	0	0
T1	20678	6	0	0
T2	244474	62	0	0
T3	17159	21	0	0
T4	13228	14	0	0
T5	20231	2	0	0
T6	180038	55	0	0
T7	14779	6	0	0
T8	85730	52	0	0
T9	7047	1	0	0
T10	24547	17	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51664008	20949	0	0
T1	20678	6	0	0
T2	244474	62	0	0
T3	17159	21	0	0
T4	13228	14	0	0
T5	20231	2	0	0
T6	180038	55	0	0
T7	14779	6	0	0
T8	85730	52	0	0
T9	7047	1	0	0
T10	24547	17	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	203	0	0
T6	5464	1	0	0
T7	441	0	0	0
T8	2632	0	0	0
T9	211	0	0	0
T10	734	0	0	0
T11	442	0	0	0
T12	690	0	0	0
T21	2676	0	0	0
T22	301	0	0	0
T50	0	5	0	0
T53	0	1	0	0
T57	0	3	0	0
T58	0	2	0	0
T61	198	0	0	0
T96	0	3	0	0
T103	0	1	0	0
T105	0	7	0	0
T130	0	1	0	0
T134	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1565791	8231	0	0
T1	618	2	0	0
T2	7403	26	0	0
T3	513	1	0	0
T4	395	1	0	0
T5	606	2	0	0
T6	5464	23	0	0
T7	441	2	0	0
T8	2632	20	0	0
T9	211	1	0	0
T10	734	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	20949	0	0
T1	4962	6	0	0
T2	58670	62	0	0
T3	4117	21	0	0
T4	3174	14	0	0
T5	4855	2	0	0
T6	43217	55	0	0
T7	3546	6	0	0
T8	20569	52	0	0
T9	1690	1	0	0
T10	5890	17	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12398970	20949	0	0
T1	4962	6	0	0
T2	58670	62	0	0
T3	4117	21	0	0
T4	3174	14	0	0
T5	4855	2	0	0
T6	43217	55	0	0
T7	3546	6	0	0
T8	20569	52	0	0
T9	1690	1	0	0
T10	5890	17	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985737	20949	0	0
T1	4674	6	0	0
T2	53730	62	0	0
T3	2849	21	0	0
T4	2247	14	0	0
T5	4692	2	0	0
T6	38026	55	0	0
T7	3260	6	0	0
T8	16070	52	0	0
T9	1672	1	0	0
T10	4949	17	0	0