Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	648758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

389298

1

T2

1204

T3

1126

T6

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	553811	1			T2	1786		T3	1707		T4	1
values[0x0]	241773	1			T2	703		T3	641		T6	102
values[0x1]	242472	1			T2	672		T3	653		T6	91

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	544562	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

493494

1

T2

1524

T3

1423

T6

163

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3423	1			T3	15		T7	8		T9	12
valid_sources[0x01]	3398	1			T3	14		T7	11		T9	10
valid_sources[0x02]	3531	1			T3	11		T7	13		T9	4
valid_sources[0x03]	3400	1			T2	154		T3	12		T7	10
valid_sources[0x04]	3808	1			T3	12		T6	31		T7	3
valid_sources[0x05]	3421	1			T3	8		T7	9		T9	17
valid_sources[0x06]	3752	1			T3	12		T6	59		T7	21
valid_sources[0x07]	3090	1			T3	9		T7	5		T9	13
valid_sources[0x08]	3810	1			T3	10		T7	14		T9	9
valid_sources[0x09]	3822	1			T3	8		T7	3		T9	13
valid_sources[0x0a]	8826	1			T2	6		T3	10		T7	11
valid_sources[0x0b]	3684	1			T3	8		T7	10		T9	10
valid_sources[0x0c]	3941	1			T2	4		T3	12		T7	1
valid_sources[0x0d]	3392	1			T3	15		T7	8		T9	12
valid_sources[0x0e]	3994	1			T3	16		T7	7		T9	9
valid_sources[0x0f]	3337	1			T3	12		T7	11		T8	9
valid_sources[0x10]	4347	1			T3	16		T7	7		T8	2
valid_sources[0x11]	4148	1			T3	12		T7	2		T8	7
valid_sources[0x12]	3745	1			T3	14		T7	9		T8	1
valid_sources[0x13]	3444	1			T3	9		T7	13		T9	7
valid_sources[0x14]	3434	1			T3	8		T7	3		T9	15
valid_sources[0x15]	3649	1			T3	8		T7	4		T8	2
valid_sources[0x16]	3656	1			T3	12		T7	5		T9	10
valid_sources[0x17]	3339	1			T3	20		T7	13		T9	7
valid_sources[0x18]	3165	1			T2	238		T3	19		T7	17
valid_sources[0x19]	6100	1			T3	22		T7	2		T8	1
valid_sources[0x1a]	4229	1			T3	18		T7	6		T9	9
valid_sources[0x1b]	3130	1			T3	5		T7	3		T8	1
valid_sources[0x1c]	3005	1			T3	12		T7	1		T9	10
valid_sources[0x1d]	3063	1			T3	15		T7	2		T9	16
valid_sources[0x1e]	4367	1			T3	14		T7	15		T9	16
valid_sources[0x1f]	3972	1			T3	7		T7	9		T9	13
valid_sources[0x20]	4521	1			T3	12		T7	11		T8	2
valid_sources[0x21]	4761	1			T3	15		T9	12		T12	7
valid_sources[0x22]	3942	1			T3	13		T7	16		T9	7
valid_sources[0x23]	3535	1			T3	15		T9	7		T23	23
valid_sources[0x24]	7873	1			T3	14		T7	16		T8	2
valid_sources[0x25]	6077	1			T3	11		T7	9		T8	5
valid_sources[0x26]	4910	1			T2	322		T3	12		T7	16
valid_sources[0x27]	3924	1			T2	179		T3	9		T7	8
valid_sources[0x28]	3742	1			T2	1		T3	6		T7	6
valid_sources[0x29]	7418	1			T3	6		T7	47		T9	14
valid_sources[0x2a]	3104	1			T3	10		T7	29		T8	2
valid_sources[0x2b]	6455	1			T3	7		T7	10		T8	3
valid_sources[0x2c]	4269	1			T3	11		T7	30		T8	2
valid_sources[0x2d]	4211	1			T3	8		T7	8		T9	20
valid_sources[0x2e]	3635	1			T3	14		T7	10		T9	8
valid_sources[0x2f]	3365	1			T3	10		T7	3		T8	1
valid_sources[0x30]	4352	1			T3	15		T7	11		T9	11
valid_sources[0x31]	6464	1			T3	16		T7	11		T9	12
valid_sources[0x32]	3743	1			T3	12		T7	18		T9	5
valid_sources[0x33]	3343	1			T3	21		T7	20		T8	3
valid_sources[0x34]	4007	1			T3	7		T7	12		T9	17
valid_sources[0x35]	4065	1			T3	18		T7	9		T8	1
valid_sources[0x36]	3632	1			T3	9		T7	3		T9	11
valid_sources[0x37]	3748	1			T3	13		T7	23		T8	7
valid_sources[0x38]	3769	1			T3	13		T7	4		T9	13
valid_sources[0x39]	3812	1			T3	16		T7	9		T8	3
valid_sources[0x3a]	3197	1			T3	16		T7	14		T8	5
valid_sources[0x3b]	4612	1			T3	11		T7	11		T8	3
valid_sources[0x3c]	4388	1			T3	14		T7	15		T9	14
valid_sources[0x3d]	3743	1			T3	20		T7	29		T9	10
valid_sources[0x3e]	3772	1			T3	8		T7	5		T8	2
valid_sources[0x3f]	4081	1			T3	9		T7	12		T9	11
valid_sources[0x40]	3330	1			T3	7		T7	9		T9	13
valid_sources[0x41]	3852	1			T3	11		T7	17		T8	18
valid_sources[0x42]	3528	1			T3	5		T7	4		T9	10
valid_sources[0x43]	4026	1			T2	7		T3	20		T7	19
valid_sources[0x44]	4328	1			T3	15		T7	21		T9	13
valid_sources[0x45]	3456	1			T3	10		T7	7		T9	14
valid_sources[0x46]	3866	1			T3	8		T7	7		T9	13
valid_sources[0x47]	3961	1			T3	11		T7	19		T9	7
valid_sources[0x48]	3328	1			T3	14		T7	12		T8	2
valid_sources[0x49]	3528	1			T3	10		T7	11		T9	8
valid_sources[0x4a]	6513	1			T3	12		T7	5		T9	18
valid_sources[0x4b]	3873	1			T3	16		T7	2		T9	7
valid_sources[0x4c]	3629	1			T3	14		T7	12		T9	8
valid_sources[0x4d]	4648	1			T3	17		T7	6		T8	5
valid_sources[0x4e]	3690	1			T3	10		T7	11		T9	13
valid_sources[0x4f]	3689	1			T3	13		T7	17		T8	2
valid_sources[0x50]	4176	1			T3	9		T7	12		T9	13
valid_sources[0x51]	4312	1			T2	53		T3	8		T7	11
valid_sources[0x52]	3965	1			T3	10		T6	74		T7	8
valid_sources[0x53]	3655	1			T3	11		T7	1		T9	12
valid_sources[0x54]	4341	1			T3	18		T7	14		T8	1
valid_sources[0x55]	3484	1			T3	5		T7	6		T9	12
valid_sources[0x56]	3640	1			T2	283		T3	11		T7	9
valid_sources[0x57]	3421	1			T3	12		T7	8		T9	11
valid_sources[0x58]	3319	1			T3	12		T7	2		T9	8
valid_sources[0x59]	3647	1			T3	15		T7	4		T9	18
valid_sources[0x5a]	3869	1			T3	6		T7	14		T9	13
valid_sources[0x5b]	3840	1			T3	16		T7	9		T9	8
valid_sources[0x5c]	4734	1			T3	8		T7	16		T8	3
valid_sources[0x5d]	4525	1			T3	14		T7	13		T8	3
valid_sources[0x5e]	3495	1			T3	8		T7	1		T9	11
valid_sources[0x5f]	3596	1			T2	152		T3	14		T7	6
valid_sources[0x60]	6247	1			T3	12		T7	8		T8	2
valid_sources[0x61]	4016	1			T2	155		T3	9		T7	19
valid_sources[0x62]	3831	1			T3	13		T9	11		T12	6
valid_sources[0x63]	3849	1			T3	7		T7	17		T9	10
valid_sources[0x64]	5068	1			T3	23		T7	2		T9	10
valid_sources[0x65]	3900	1			T3	15		T7	13		T9	14
valid_sources[0x66]	3422	1			T3	11		T7	4		T8	1
valid_sources[0x67]	3487	1			T3	21		T7	9		T9	13
valid_sources[0x68]	3666	1			T3	16		T7	4		T8	8
valid_sources[0x69]	4764	1			T3	12		T7	7		T9	12
valid_sources[0x6a]	3263	1			T3	8		T7	4		T9	12
valid_sources[0x6b]	3196	1			T3	7		T7	14		T9	8
valid_sources[0x6c]	3113	1			T3	15		T7	8		T9	8
valid_sources[0x6d]	3507	1			T3	11		T7	5		T8	1
valid_sources[0x6e]	3632	1			T3	12		T7	21		T8	1
valid_sources[0x6f]	4615	1			T3	14		T7	17		T8	2
valid_sources[0x70]	5560	1			T2	58		T3	10		T7	10
valid_sources[0x71]	4630	1			T3	6		T7	8		T9	22
valid_sources[0x72]	4211	1			T3	8		T7	11		T8	5
valid_sources[0x73]	3685	1			T3	9		T7	11		T9	16
valid_sources[0x74]	3153	1			T3	11		T7	7		T8	1
valid_sources[0x75]	4847	1			T3	13		T7	8		T9	8
valid_sources[0x76]	4066	1			T3	12		T7	7		T9	8
valid_sources[0x77]	3458	1			T3	13		T7	22		T8	4
valid_sources[0x78]	3592	1			T3	16		T7	10		T9	8
valid_sources[0x79]	4662	1			T3	11		T7	6		T9	8
valid_sources[0x7a]	3818	1			T3	14		T7	6		T9	15
valid_sources[0x7b]	3529	1			T3	14		T7	7		T8	4
valid_sources[0x7c]	4151	1			T3	13		T7	10		T8	10
valid_sources[0x7d]	3948	1			T3	5		T7	5		T9	15
valid_sources[0x7e]	3725	1			T3	14		T7	19		T8	2
valid_sources[0x7f]	4281	1			T3	6		T6	29		T7	4
valid_sources[0x80]	4878	1			T3	12		T7	14		T9	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

260149

1

T2

837

T3

806

T6

90

values[0x0]

all_enables

biggest_size

84428

1

T2

257

T3

216

T6

25

values[0x1]

all_enables

biggest_size

44721

1

T2

110

T3

104

T6

17