Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T33
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T42,T78
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T42,T78
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T42
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T42,T78
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T33
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T33,T42
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13326673	14771	0	0
gen_assertions[0].RstEnOn_A	13326673	1172	0	0
gen_assertions[0].RstNOff_A	13326673	14771	0	0
gen_assertions[0].RstNOn_A	13326673	1172	0	0
gen_assertions[1].RstEnOff_A	53306719	13431	0	0
gen_assertions[1].RstEnOn_A	53306719	1131	0	0
gen_assertions[1].RstNOff_A	53306719	13431	0	0
gen_assertions[1].RstNOn_A	53306719	1131	0	0
gen_assertions[2].RstEnOff_A	26654131	13515	0	0
gen_assertions[2].RstEnOn_A	26654131	1140	0	0
gen_assertions[2].RstNOff_A	26654131	13515	0	0
gen_assertions[2].RstNOn_A	26654131	1140	0	0
gen_assertions[3].RstEnOff_A	26654149	13571	0	0
gen_assertions[3].RstEnOn_A	26654149	1181	0	0
gen_assertions[3].RstNOff_A	26654149	13571	0	0
gen_assertions[3].RstNOn_A	26654149	1181	0	0
gen_assertions[4].RstEnOff_A	1683368	22456	0	0
gen_assertions[4].RstEnOn_A	1683368	1233	0	0
gen_assertions[4].RstNOff_A	1683368	22456	0	0
gen_assertions[4].RstNOn_A	1683368	1233	0	0
gen_assertions[5].RstEnOff_A	13326673	15049	0	0
gen_assertions[5].RstEnOn_A	13326673	1284	0	0
gen_assertions[5].RstNOff_A	13326673	15049	0	0
gen_assertions[5].RstNOn_A	13326673	1284	0	0
gen_assertions[6].RstEnOff_A	13326673	15110	0	0
gen_assertions[6].RstEnOn_A	13326673	1352	0	0
gen_assertions[6].RstNOff_A	13326673	15110	0	0
gen_assertions[6].RstNOn_A	13326673	1352	0	0
gen_assertions[7].RstEnOff_A	13326673	15151	0	0
gen_assertions[7].RstEnOn_A	13326673	1387	0	0
gen_assertions[7].RstNOff_A	13326673	15151	0	0
gen_assertions[7].RstNOn_A	13326673	1387	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	14771	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	4	0	0
T7	29774	34	0	0
T8	2812	5	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	4	0	0
T13	0	18	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1172	0	0
T8	2812	1	0	0
T9	22633	0	0	0
T10	3457	0	0	0
T11	52371	0	0	0
T12	3481	4	0	0
T13	4113	11	0	0
T14	4330	0	0	0
T15	2914	0	0	0
T23	40574	0	0	0
T33	5289	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T47	0	8	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T78	0	17	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	14771	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	4	0	0
T7	29774	34	0	0
T8	2812	5	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	4	0	0
T13	0	18	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1172	0	0
T8	2812	1	0	0
T9	22633	0	0	0
T10	3457	0	0	0
T11	52371	0	0	0
T12	3481	4	0	0
T13	4113	11	0	0
T14	4330	0	0	0
T15	2914	0	0	0
T23	40574	0	0	0
T33	5289	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T47	0	8	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T78	0	17	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53306719	13431	0	0
T2	198997	38	0	0
T3	92129	34	0	0
T4	11452	0	0	0
T5	23267	0	0	0
T6	23614	3	0	0
T7	119106	31	0	0
T8	11252	4	0	0
T9	90545	37	0	0
T10	13835	4	0	0
T11	209465	68	0	0
T12	0	7	0	0
T13	0	14	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53306719	1131	0	0
T12	13928	7	0	0
T13	16455	4	0	0
T14	17321	0	0	0
T15	11660	0	0	0
T23	162281	0	0	0
T33	21164	1	0	0
T34	11063	0	0	0
T35	6194	0	0	0
T36	11428	0	0	0
T42	901099	0	0	0
T47	0	11	0	0
T50	0	2	0	0
T51	0	2	0	0
T54	0	3	0	0
T78	0	20	0	0
T79	0	3	0	0
T80	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53306719	13431	0	0
T2	198997	38	0	0
T3	92129	34	0	0
T4	11452	0	0	0
T5	23267	0	0	0
T6	23614	3	0	0
T7	119106	31	0	0
T8	11252	4	0	0
T9	90545	37	0	0
T10	13835	4	0	0
T11	209465	68	0	0
T12	0	7	0	0
T13	0	14	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53306719	1131	0	0
T12	13928	7	0	0
T13	16455	4	0	0
T14	17321	0	0	0
T15	11660	0	0	0
T23	162281	0	0	0
T33	21164	1	0	0
T34	11063	0	0	0
T35	6194	0	0	0
T36	11428	0	0	0
T42	901099	0	0	0
T47	0	11	0	0
T50	0	2	0	0
T51	0	2	0	0
T54	0	3	0	0
T78	0	20	0	0
T79	0	3	0	0
T80	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654131	13515	0	0
T2	99507	38	0	0
T3	46060	34	0	0
T4	5725	0	0	0
T5	11635	0	0	0
T6	11809	3	0	0
T7	59555	31	0	0
T8	5626	4	0	0
T9	45270	37	0	0
T10	6916	4	0	0
T11	104747	68	0	0
T12	0	8	0	0
T13	0	14	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654131	1140	0	0
T12	6964	8	0	0
T13	8228	0	0	0
T14	8660	0	0	0
T15	5830	0	0	0
T23	81143	0	0	0
T33	10581	0	0	0
T34	5535	0	0	0
T35	3097	0	0	0
T36	5713	0	0	0
T42	450570	2	0	0
T47	0	9	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T54	0	3	0	0
T78	0	18	0	0
T79	0	4	0	0
T80	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654131	13515	0	0
T2	99507	38	0	0
T3	46060	34	0	0
T4	5725	0	0	0
T5	11635	0	0	0
T6	11809	3	0	0
T7	59555	31	0	0
T8	5626	4	0	0
T9	45270	37	0	0
T10	6916	4	0	0
T11	104747	68	0	0
T12	0	8	0	0
T13	0	14	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654131	1140	0	0
T12	6964	8	0	0
T13	8228	0	0	0
T14	8660	0	0	0
T15	5830	0	0	0
T23	81143	0	0	0
T33	10581	0	0	0
T34	5535	0	0	0
T35	3097	0	0	0
T36	5713	0	0	0
T42	450570	2	0	0
T47	0	9	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T54	0	3	0	0
T78	0	18	0	0
T79	0	4	0	0
T80	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654149	13571	0	0
T2	99499	38	0	0
T3	46061	34	0	0
T4	5726	0	0	0
T5	11634	0	0	0
T6	11811	3	0	0
T7	59561	31	0	0
T8	5627	4	0	0
T9	45265	37	0	0
T10	6918	4	0	0
T11	104742	68	0	0
T12	0	8	0	0
T13	0	14	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654149	1181	0	0
T12	6964	8	0	0
T13	8227	0	0	0
T14	8660	0	0	0
T15	5830	0	0	0
T23	81146	0	0	0
T33	10582	0	0	0
T34	5533	0	0	0
T35	3096	0	0	0
T36	5713	0	0	0
T42	450586	1	0	0
T47	0	13	0	0
T50	0	3	0	0
T54	0	4	0	0
T78	0	18	0	0
T79	0	5	0	0
T81	0	52	0	0
T82	0	7	0	0
T83	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654149	13571	0	0
T2	99499	38	0	0
T3	46061	34	0	0
T4	5726	0	0	0
T5	11634	0	0	0
T6	11811	3	0	0
T7	59561	31	0	0
T8	5627	4	0	0
T9	45265	37	0	0
T10	6918	4	0	0
T11	104742	68	0	0
T12	0	8	0	0
T13	0	14	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654149	1181	0	0
T12	6964	8	0	0
T13	8227	0	0	0
T14	8660	0	0	0
T15	5830	0	0	0
T23	81146	0	0	0
T33	10582	0	0	0
T34	5533	0	0	0
T35	3096	0	0	0
T36	5713	0	0	0
T42	450586	1	0	0
T47	0	13	0	0
T50	0	3	0	0
T54	0	4	0	0
T78	0	18	0	0
T79	0	5	0	0
T81	0	52	0	0
T82	0	7	0	0
T83	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	22456	0	0
T1	730	2	0	0
T2	6302	62	0	0
T3	2937	58	0	0
T4	357	2	0	0
T5	729	2	0	0
T6	736	6	0	0
T7	3783	49	0	0
T8	350	6	0	0
T9	2902	58	0	0
T10	431	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	1233	0	0
T6	736	1	0	0
T7	3783	0	0	0
T8	350	0	0	0
T9	2902	0	0	0
T10	431	0	0	0
T11	6560	0	0	0
T12	433	10	0	0
T13	513	0	0	0
T14	539	0	0	0
T23	5148	0	0	0
T42	0	1	0	0
T47	0	9	0	0
T50	0	5	0	0
T54	0	6	0	0
T78	0	19	0	0
T79	0	6	0	0
T81	0	52	0	0
T82	0	8	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	22456	0	0
T1	730	2	0	0
T2	6302	62	0	0
T3	2937	58	0	0
T4	357	2	0	0
T5	729	2	0	0
T6	736	6	0	0
T7	3783	49	0	0
T8	350	6	0	0
T9	2902	58	0	0
T10	431	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	1233	0	0
T6	736	1	0	0
T7	3783	0	0	0
T8	350	0	0	0
T9	2902	0	0	0
T10	431	0	0	0
T11	6560	0	0	0
T12	433	10	0	0
T13	513	0	0	0
T14	539	0	0	0
T23	5148	0	0	0
T42	0	1	0	0
T47	0	9	0	0
T50	0	5	0	0
T54	0	6	0	0
T78	0	19	0	0
T79	0	6	0	0
T81	0	52	0	0
T82	0	8	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	15049	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	4	0	0
T7	29774	34	0	0
T8	2812	4	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	13	0	0
T13	0	18	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1284	0	0
T12	3481	13	0	0
T13	4113	0	0	0
T14	4330	0	0	0
T15	2914	0	0	0
T23	40574	0	0	0
T33	5289	0	0	0
T34	2766	0	0	0
T35	1547	0	0	0
T36	2856	0	0	0
T42	225284	2	0	0
T47	0	10	0	0
T50	0	6	0	0
T54	0	7	0	0
T78	0	20	0	0
T79	0	7	0	0
T81	0	47	0	0
T82	0	9	0	0
T83	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	15049	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	4	0	0
T7	29774	34	0	0
T8	2812	4	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	13	0	0
T13	0	18	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1284	0	0
T12	3481	13	0	0
T13	4113	0	0	0
T14	4330	0	0	0
T15	2914	0	0	0
T23	40574	0	0	0
T33	5289	0	0	0
T34	2766	0	0	0
T35	1547	0	0	0
T36	2856	0	0	0
T42	225284	2	0	0
T47	0	10	0	0
T50	0	6	0	0
T54	0	7	0	0
T78	0	20	0	0
T79	0	7	0	0
T81	0	47	0	0
T82	0	9	0	0
T83	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	15110	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	5	0	0
T7	29774	34	0	0
T8	2812	4	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	13	0	0
T13	0	18	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1352	0	0
T6	5903	1	0	0
T7	29774	0	0	0
T8	2812	0	0	0
T9	22633	0	0	0
T10	3457	0	0	0
T11	52371	0	0	0
T12	3481	13	0	0
T13	4113	0	0	0
T14	4330	0	0	0
T23	40574	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	0	2	0	0
T47	0	11	0	0
T50	0	7	0	0
T54	0	7	0	0
T78	0	20	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	15110	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	5	0	0
T7	29774	34	0	0
T8	2812	4	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	13	0	0
T13	0	18	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1352	0	0
T6	5903	1	0	0
T7	29774	0	0	0
T8	2812	0	0	0
T9	22633	0	0	0
T10	3457	0	0	0
T11	52371	0	0	0
T12	3481	13	0	0
T13	4113	0	0	0
T14	4330	0	0	0
T23	40574	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	0	2	0	0
T47	0	11	0	0
T50	0	7	0	0
T54	0	7	0	0
T78	0	20	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	15151	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	4	0	0
T7	29774	34	0	0
T8	2812	4	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	15	0	0
T13	0	18	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1387	0	0
T12	3481	15	0	0
T13	4113	0	0	0
T14	4330	0	0	0
T15	2914	0	0	0
T23	40574	0	0	0
T33	5289	1	0	0
T34	2766	0	0	0
T35	1547	0	0	0
T36	2856	0	0	0
T42	225284	1	0	0
T47	0	11	0	0
T50	0	7	0	0
T54	0	9	0	0
T78	0	20	0	0
T79	0	8	0	0
T81	0	47	0	0
T82	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	15151	0	0
T2	49756	40	0	0
T3	23031	36	0	0
T4	2863	0	0	0
T5	5816	0	0	0
T6	5903	4	0	0
T7	29774	34	0	0
T8	2812	4	0	0
T9	22633	38	0	0
T10	3457	4	0	0
T11	52371	75	0	0
T12	0	15	0	0
T13	0	18	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	1387	0	0
T12	3481	15	0	0
T13	4113	0	0	0
T14	4330	0	0	0
T15	2914	0	0	0
T23	40574	0	0	0
T33	5289	1	0	0
T34	2766	0	0	0
T35	1547	0	0	0
T36	2856	0	0	0
T42	225284	1	0	0
T47	0	11	0	0
T50	0	7	0	0
T54	0	9	0	0
T78	0	20	0	0
T79	0	8	0	0
T81	0	47	0	0
T82	0	10	0	0