Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12565764	7245	0	0
alert_regwen_rd_A	12565764	5353	0	0
cpu_regwen_rd_A	12565764	5313	0	0
sw_rst_ctrl_n_0_rd_A	12565764	10922	0	0
sw_rst_ctrl_n_1_rd_A	12565764	11104	0	0
sw_rst_ctrl_n_2_rd_A	12565764	11336	0	0
sw_rst_ctrl_n_3_rd_A	12565764	11036	0	0
sw_rst_ctrl_n_4_rd_A	12565764	10958	0	0
sw_rst_ctrl_n_5_rd_A	12565764	10979	0	0
sw_rst_ctrl_n_6_rd_A	12565764	11104	0	0
sw_rst_ctrl_n_7_rd_A	12565764	10874	0	0
sw_rst_regwen_0_rd_A	12565764	5901	0	0
sw_rst_regwen_1_rd_A	12565764	6013	0	0
sw_rst_regwen_2_rd_A	12565764	6248	0	0
sw_rst_regwen_3_rd_A	12565764	6097	0	0
sw_rst_regwen_4_rd_A	12565764	5953	0	0
sw_rst_regwen_5_rd_A	12565764	6137	0	0
sw_rst_regwen_6_rd_A	12565764	6127	0	0
sw_rst_regwen_7_rd_A	12565764	6252	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	7245	0	0
T55	12352	1	0	0
T56	9860	2	0	0
T58	6188	299	0	0
T59	3118	313	0	0
T60	7296	149	0	0
T61	20733	2	0	0
T85	22476	3	0	0
T86	2277	114	0	0
T91	11319	2	0	0
T122	12284	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	5353	0	0
T2	44853	84	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	0	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	55	0	0
T42	0	293	0	0
T78	0	541	0	0
T81	0	164	0	0
T93	0	72	0	0
T94	0	20	0	0
T95	0	11	0	0
T96	0	41	0	0
T99	0	99	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	5313	0	0
T2	44853	90	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	0	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	46	0	0
T42	0	342	0	0
T78	0	601	0	0
T81	0	94	0	0
T93	0	81	0	0
T94	0	4	0	0
T95	0	43	0	0
T96	0	60	0	0
T99	0	98	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	10922	0	0
T2	44853	94	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	26	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	55	0	0
T33	0	9	0	0
T42	0	309	0	0
T54	0	126	0	0
T78	0	805	0	0
T93	0	55	0	0
T94	0	16	0	0
T95	0	29	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	11104	0	0
T2	44853	67	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	6	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	43	0	0
T33	0	14	0	0
T42	0	285	0	0
T54	0	118	0	0
T78	0	821	0	0
T93	0	85	0	0
T94	0	7	0	0
T95	0	27	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	11336	0	0
T2	44853	94	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	11	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	27	0	0
T33	0	14	0	0
T42	0	335	0	0
T54	0	130	0	0
T78	0	855	0	0
T93	0	76	0	0
T94	0	16	0	0
T95	0	42	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	11036	0	0
T2	44853	89	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	10	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	38	0	0
T33	0	7	0	0
T42	0	323	0	0
T54	0	103	0	0
T78	0	783	0	0
T93	0	68	0	0
T94	0	35	0	0
T95	0	36	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	10958	0	0
T2	44853	71	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	16	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	64	0	0
T33	0	11	0	0
T42	0	292	0	0
T54	0	147	0	0
T78	0	853	0	0
T93	0	96	0	0
T94	0	13	0	0
T95	0	35	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	10979	0	0
T2	44853	69	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	6	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	51	0	0
T33	0	2	0	0
T42	0	245	0	0
T54	0	117	0	0
T78	0	785	0	0
T93	0	76	0	0
T94	0	19	0	0
T95	0	53	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	11104	0	0
T2	44853	68	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	19	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	44	0	0
T33	0	7	0	0
T42	0	310	0	0
T54	0	123	0	0
T78	0	780	0	0
T93	0	74	0	0
T94	0	13	0	0
T95	0	16	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	10874	0	0
T2	44853	76	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	22	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	57	0	0
T33	0	6	0	0
T42	0	314	0	0
T54	0	147	0	0
T78	0	803	0	0
T93	0	101	0	0
T94	0	42	0	0
T95	0	17	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	5901	0	0
T2	44853	67	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	6	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	55	0	0
T42	0	344	0	0
T54	0	39	0	0
T78	0	567	0	0
T93	0	79	0	0
T94	0	15	0	0
T95	0	36	0	0
T96	0	56	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	6013	0	0
T2	44853	91	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	7	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	58	0	0
T42	0	319	0	0
T54	0	14	0	0
T78	0	610	0	0
T93	0	76	0	0
T94	0	13	0	0
T95	0	28	0	0
T96	0	48	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	6248	0	0
T2	44853	70	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	4	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	52	0	0
T33	0	2	0	0
T42	0	300	0	0
T54	0	29	0	0
T78	0	534	0	0
T93	0	67	0	0
T94	0	43	0	0
T95	0	32	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	6097	0	0
T2	44853	63	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	8	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	40	0	0
T33	0	10	0	0
T42	0	343	0	0
T54	0	23	0	0
T78	0	538	0	0
T93	0	57	0	0
T94	0	18	0	0
T95	0	15	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	5953	0	0
T2	44853	87	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	8	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	41	0	0
T33	0	3	0	0
T42	0	326	0	0
T54	0	30	0	0
T78	0	515	0	0
T93	0	65	0	0
T94	0	17	0	0
T95	0	31	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	6137	0	0
T2	44853	35	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	6	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	39	0	0
T33	0	7	0	0
T42	0	293	0	0
T54	0	46	0	0
T78	0	611	0	0
T93	0	63	0	0
T94	0	41	0	0
T95	0	53	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	6127	0	0
T2	44853	65	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	5	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	70	0	0
T33	0	4	0	0
T42	0	290	0	0
T54	0	26	0	0
T78	0	542	0	0
T93	0	86	0	0
T94	0	9	0	0
T95	0	23	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12565764	6252	0	0
T2	44853	72	0	0
T3	17546	0	0	0
T4	2724	0	0	0
T5	5463	0	0	0
T6	5757	2	0	0
T7	25699	0	0	0
T8	2522	0	0	0
T9	17620	0	0	0
T10	3170	0	0	0
T11	49026	0	0	0
T23	0	42	0	0
T42	0	276	0	0
T54	0	44	0	0
T78	0	603	0	0
T93	0	77	0	0
T94	0	55	0	0
T95	0	44	0	0
T96	0	49	0	0