Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55528821	8853	0	0
CascadeEffAonToRstPorAboveRise_A	55528821	8853	0	0
CascadeEffAonToRstPorIoAboveFall_A	53306719	8853	0	0
CascadeEffAonToRstPorIoAboveRise_A	53306719	8853	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26654131	8853	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26654131	8853	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13326673	8853	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13326673	8853	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26654149	8853	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26654149	8853	0	0
CascadeLcToLcAboveFall_A	55528821	22663	0	0
CascadeLcToLcAboveRise_A	55528821	22663	0	0
CascadeLcToLcAonAboveFall_A	1683368	22663	0	0
CascadeLcToLcAonAboveRise_A	1683368	22663	0	0
CascadeLcToLcShadowedAboveFall_A	55528821	22663	0	0
CascadeLcToLcShadowedAboveRise_A	55528821	22663	0	0
CascadePorToAonAboveFall_A	1683368	6946	0	0
CascadeSysToSysAboveFall_A	55528821	22663	0	0
CascadeSysToSysAboveRise_A	55528821	22663	0	0
ScanRstToAonRise_A	1683368	226	0	0
StablePorToAonRise_A	1683368	8853	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11755086	22663	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11755086	22663	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11755086	22663	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11755086	22663	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13326673	22663	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13326673	22663	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11755086	22663	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11755086	22663	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11755086	22663	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11755086	22663	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	8853	0	0
T1	24300	8	0	0
T2	207287	22	0	0
T3	95958	22	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	2	0	0
T7	124069	15	0	0
T8	11724	2	0	0
T9	94310	20	0	0
T10	14411	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	8853	0	0
T1	24300	8	0	0
T2	207287	22	0	0
T3	95958	22	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	2	0	0
T7	124069	15	0	0
T8	11724	2	0	0
T9	94310	20	0	0
T10	14411	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53306719	8853	0	0
T1	23337	8	0	0
T2	198997	22	0	0
T3	92129	22	0	0
T4	11452	2	0	0
T5	23267	8	0	0
T6	23614	2	0	0
T7	119106	15	0	0
T8	11252	2	0	0
T9	90545	20	0	0
T10	13835	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53306719	8853	0	0
T1	23337	8	0	0
T2	198997	22	0	0
T3	92129	22	0	0
T4	11452	2	0	0
T5	23267	8	0	0
T6	23614	2	0	0
T7	119106	15	0	0
T8	11252	2	0	0
T9	90545	20	0	0
T10	13835	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654131	8853	0	0
T1	11663	8	0	0
T2	99507	22	0	0
T3	46060	22	0	0
T4	5725	2	0	0
T5	11635	8	0	0
T6	11809	2	0	0
T7	59555	15	0	0
T8	5626	2	0	0
T9	45270	20	0	0
T10	6916	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654131	8853	0	0
T1	11663	8	0	0
T2	99507	22	0	0
T3	46060	22	0	0
T4	5725	2	0	0
T5	11635	8	0	0
T6	11809	2	0	0
T7	59555	15	0	0
T8	5626	2	0	0
T9	45270	20	0	0
T10	6916	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	8853	0	0
T1	5830	8	0	0
T2	49756	22	0	0
T3	23031	22	0	0
T4	2863	2	0	0
T5	5816	8	0	0
T6	5903	2	0	0
T7	29774	15	0	0
T8	2812	2	0	0
T9	22633	20	0	0
T10	3457	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	8853	0	0
T1	5830	8	0	0
T2	49756	22	0	0
T3	23031	22	0	0
T4	2863	2	0	0
T5	5816	8	0	0
T6	5903	2	0	0
T7	29774	15	0	0
T8	2812	2	0	0
T9	22633	20	0	0
T10	3457	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654149	8853	0	0
T1	11661	8	0	0
T2	99499	22	0	0
T3	46061	22	0	0
T4	5726	2	0	0
T5	11634	8	0	0
T6	11811	2	0	0
T7	59561	15	0	0
T8	5627	2	0	0
T9	45265	20	0	0
T10	6918	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26654149	8853	0	0
T1	11661	8	0	0
T2	99499	22	0	0
T3	46061	22	0	0
T4	5726	2	0	0
T5	11634	8	0	0
T6	11811	2	0	0
T7	59561	15	0	0
T8	5627	2	0	0
T9	45265	20	0	0
T10	6918	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	22663	0	0
T1	24300	8	0	0
T2	207287	62	0	0
T3	95958	58	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	6	0	0
T7	124069	49	0	0
T8	11724	6	0	0
T9	94310	58	0	0
T10	14411	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	22663	0	0
T1	24300	8	0	0
T2	207287	62	0	0
T3	95958	58	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	6	0	0
T7	124069	49	0	0
T8	11724	6	0	0
T9	94310	58	0	0
T10	14411	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	22663	0	0
T1	730	8	0	0
T2	6302	62	0	0
T3	2937	58	0	0
T4	357	2	0	0
T5	729	8	0	0
T6	736	6	0	0
T7	3783	49	0	0
T8	350	6	0	0
T9	2902	58	0	0
T10	431	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	22663	0	0
T1	730	8	0	0
T2	6302	62	0	0
T3	2937	58	0	0
T4	357	2	0	0
T5	729	8	0	0
T6	736	6	0	0
T7	3783	49	0	0
T8	350	6	0	0
T9	2902	58	0	0
T10	431	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	22663	0	0
T1	24300	8	0	0
T2	207287	62	0	0
T3	95958	58	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	6	0	0
T7	124069	49	0	0
T8	11724	6	0	0
T9	94310	58	0	0
T10	14411	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	22663	0	0
T1	24300	8	0	0
T2	207287	62	0	0
T3	95958	58	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	6	0	0
T7	124069	49	0	0
T8	11724	6	0	0
T9	94310	58	0	0
T10	14411	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	6946	0	0
T1	730	8	0	0
T2	6302	12	0	0
T3	2937	9	0	0
T4	357	7	0	0
T5	729	8	0	0
T6	736	1	0	0
T7	3783	8	0	0
T8	350	1	0	0
T9	2902	10	0	0
T10	431	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	22663	0	0
T1	24300	8	0	0
T2	207287	62	0	0
T3	95958	58	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	6	0	0
T7	124069	49	0	0
T8	11724	6	0	0
T9	94310	58	0	0
T10	14411	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55528821	22663	0	0
T1	24300	8	0	0
T2	207287	62	0	0
T3	95958	58	0	0
T4	11930	2	0	0
T5	24228	8	0	0
T6	24598	6	0	0
T7	124069	49	0	0
T8	11724	6	0	0
T9	94310	58	0	0
T10	14411	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	226	0	0
T3	2937	1	0	0
T4	357	0	0	0
T5	729	0	0	0
T6	736	0	0	0
T7	3783	1	0	0
T8	350	0	0	0
T9	2902	1	0	0
T10	431	0	0	0
T11	6560	0	0	0
T12	433	0	0	0
T42	0	3	0	0
T78	0	9	0	0
T81	0	2	0	0
T94	0	1	0	0
T96	0	2	0	0
T98	0	7	0	0
T104	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683368	8853	0	0
T1	730	8	0	0
T2	6302	22	0	0
T3	2937	22	0	0
T4	357	2	0	0
T5	729	8	0	0
T6	736	2	0	0
T7	3783	15	0	0
T8	350	2	0	0
T9	2902	20	0	0
T10	431	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	22663	0	0
T1	5830	8	0	0
T2	49756	62	0	0
T3	23031	58	0	0
T4	2863	2	0	0
T5	5816	8	0	0
T6	5903	6	0	0
T7	29774	49	0	0
T8	2812	6	0	0
T9	22633	58	0	0
T10	3457	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13326673	22663	0	0
T1	5830	8	0	0
T2	49756	62	0	0
T3	23031	58	0	0
T4	2863	2	0	0
T5	5816	8	0	0
T6	5903	6	0	0
T7	29774	49	0	0
T8	2812	6	0	0
T9	22633	58	0	0
T10	3457	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11755086	22663	0	0
T1	5671	8	0	0
T2	44853	62	0	0
T3	17546	58	0	0
T4	2724	2	0	0
T5	5463	8	0	0
T6	5757	6	0	0
T7	25699	49	0	0
T8	2522	6	0	0
T9	17620	58	0	0
T10	3170	6	0	0