Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

386250

1

T1

1095

T2

74

T3

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	550660	1			T1	1500		T2	99		T3	161
values[0x0]	239659	1			T1	816		T2	56		T3	88
values[0x1]	239903	1			T1	884		T2	57		T3	82

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	539939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

490283

1

T1

1388

T2

98

T3

154

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3500	1			T1	15		T9	1		T10	12
valid_sources[0x01]	3591	1			T1	27		T9	1		T10	18
valid_sources[0x02]	4090	1			T1	1		T8	3		T10	10
valid_sources[0x03]	6726	1			T1	12		T2	3		T3	6
valid_sources[0x04]	3466	1			T1	20		T3	12		T8	9
valid_sources[0x05]	2970	1			T1	13		T9	2		T10	10
valid_sources[0x06]	3795	1			T1	5		T4	168		T9	3
valid_sources[0x07]	3957	1			T1	19		T8	6		T9	1
valid_sources[0x08]	3712	1			T1	28		T2	5		T8	2
valid_sources[0x09]	4658	1			T1	29		T10	10		T22	1
valid_sources[0x0a]	3362	1			T1	13		T8	2		T9	3
valid_sources[0x0b]	3223	1			T1	14		T9	1		T10	11
valid_sources[0x0c]	3128	1			T1	12		T3	10		T10	11
valid_sources[0x0d]	3183	1			T1	21		T10	14		T22	7
valid_sources[0x0e]	4042	1			T1	11		T4	156		T9	1
valid_sources[0x0f]	4623	1			T1	11		T4	112		T9	4
valid_sources[0x10]	4296	1			T1	10		T8	2		T9	2
valid_sources[0x11]	4472	1			T1	21		T9	3		T10	13
valid_sources[0x12]	4718	1			T1	18		T8	2		T9	1
valid_sources[0x13]	3472	1			T1	13		T9	2		T10	12
valid_sources[0x14]	4206	1			T1	8		T4	1		T9	2
valid_sources[0x15]	3279	1			T1	1		T2	8		T3	2
valid_sources[0x16]	3371	1			T1	4		T10	9		T22	2
valid_sources[0x17]	4689	1			T1	8		T3	9		T8	2
valid_sources[0x18]	3610	1			T1	9		T9	1		T10	11
valid_sources[0x19]	3047	1			T1	19		T8	2		T10	23
valid_sources[0x1a]	3834	1			T1	13		T9	3		T10	20
valid_sources[0x1b]	3859	1			T4	113		T8	5		T10	10
valid_sources[0x1c]	3117	1			T1	25		T4	4		T8	1
valid_sources[0x1d]	6622	1			T1	24		T3	3		T9	1
valid_sources[0x1e]	5330	1			T1	15		T9	3		T10	14
valid_sources[0x1f]	3558	1			T1	21		T10	8		T22	6
valid_sources[0x20]	3367	1			T1	15		T9	1		T10	11
valid_sources[0x21]	3695	1			T1	9		T2	3		T3	8
valid_sources[0x22]	3307	1			T1	7		T3	6		T10	18
valid_sources[0x23]	3320	1			T1	6		T3	4		T9	1
valid_sources[0x24]	3443	1			T1	7		T9	5		T10	13
valid_sources[0x25]	4433	1			T1	4		T10	11		T22	4
valid_sources[0x26]	3923	1			T1	10		T10	13		T22	3
valid_sources[0x27]	3803	1			T1	18		T10	4		T11	4
valid_sources[0x28]	3348	1			T1	13		T2	5		T9	1
valid_sources[0x29]	3539	1			T1	12		T3	5		T9	1
valid_sources[0x2a]	3836	1			T1	18		T9	3		T10	16
valid_sources[0x2b]	4066	1			T1	8		T2	4		T9	2
valid_sources[0x2c]	4707	1			T1	26		T2	3		T9	1
valid_sources[0x2d]	3494	1			T1	9		T3	1		T10	11
valid_sources[0x2e]	3543	1			T1	1		T2	5		T3	1
valid_sources[0x2f]	3711	1			T1	19		T2	1		T3	9
valid_sources[0x30]	4677	1			T1	7		T9	1		T10	11
valid_sources[0x31]	4769	1			T1	29		T9	1		T10	6
valid_sources[0x32]	3293	1			T1	7		T3	2		T10	9
valid_sources[0x33]	2990	1			T1	26		T2	2		T9	2
valid_sources[0x34]	3576	1			T1	6		T9	2		T10	11
valid_sources[0x35]	3108	1			T1	5		T9	5		T10	11
valid_sources[0x36]	3176	1			T1	15		T2	2		T10	11
valid_sources[0x37]	4426	1			T1	9		T10	6		T22	1
valid_sources[0x38]	4131	1			T1	4		T9	2		T10	10
valid_sources[0x39]	6750	1			T1	12		T2	2		T10	9
valid_sources[0x3a]	4472	1			T1	10		T7	984		T9	3
valid_sources[0x3b]	3101	1			T1	3		T8	1		T9	2
valid_sources[0x3c]	3170	1			T1	36		T2	1		T9	1
valid_sources[0x3d]	3344	1			T1	6		T8	1		T9	1
valid_sources[0x3e]	3255	1			T1	30		T9	4		T10	14
valid_sources[0x3f]	7254	1			T1	10		T3	9		T9	1
valid_sources[0x40]	3652	1			T1	19		T8	1		T9	3
valid_sources[0x41]	6913	1			T1	11		T4	308		T8	4
valid_sources[0x42]	3493	1			T1	7		T8	7		T9	1
valid_sources[0x43]	3012	1			T1	11		T9	2		T10	11
valid_sources[0x44]	3932	1			T1	2		T3	1		T5	1
valid_sources[0x45]	3078	1			T1	14		T3	17		T10	19
valid_sources[0x46]	4051	1			T1	12		T8	5		T10	13
valid_sources[0x47]	4209	1			T1	9		T3	5		T10	12
valid_sources[0x48]	3900	1			T1	9		T9	2		T10	13
valid_sources[0x49]	4353	1			T1	6		T2	5		T3	8
valid_sources[0x4a]	4416	1			T1	39		T9	1		T10	8
valid_sources[0x4b]	4175	1			T1	11		T3	2		T9	1
valid_sources[0x4c]	4394	1			T1	7		T2	7		T3	4
valid_sources[0x4d]	4813	1			T1	9		T10	26		T22	2
valid_sources[0x4e]	4087	1			T1	13		T9	10		T10	14
valid_sources[0x4f]	4753	1			T1	3		T9	1		T10	5
valid_sources[0x50]	3491	1			T1	7		T3	1		T10	14
valid_sources[0x51]	3359	1			T1	15		T3	7		T9	4
valid_sources[0x52]	6651	1			T1	5		T3	2		T8	1
valid_sources[0x53]	3503	1			T1	13		T3	1		T10	17
valid_sources[0x54]	4505	1			T1	18		T2	5		T3	1
valid_sources[0x55]	4119	1			T1	9		T4	156		T10	17
valid_sources[0x56]	4037	1			T1	2		T2	2		T10	12
valid_sources[0x57]	5395	1			T1	2		T3	2		T8	9
valid_sources[0x58]	3707	1			T1	28		T9	1		T10	12
valid_sources[0x59]	3944	1			T1	11		T2	1		T9	1
valid_sources[0x5a]	3920	1			T1	19		T9	1		T10	9
valid_sources[0x5b]	3917	1			T1	5		T3	1		T8	3
valid_sources[0x5c]	3906	1			T1	10		T9	1		T10	7
valid_sources[0x5d]	3142	1			T1	7		T9	3		T10	14
valid_sources[0x5e]	3943	1			T1	24		T3	1		T4	113
valid_sources[0x5f]	3545	1			T1	22		T8	9		T9	3
valid_sources[0x60]	3500	1			T1	11		T3	4		T10	7
valid_sources[0x61]	3744	1			T1	5		T2	7		T3	1
valid_sources[0x62]	3697	1			T1	23		T2	2		T10	11
valid_sources[0x63]	4538	1			T1	7		T2	2		T9	2
valid_sources[0x64]	3137	1			T1	25		T3	1		T9	1
valid_sources[0x65]	4695	1			T1	14		T3	4		T9	3
valid_sources[0x66]	3813	1			T1	3		T2	5		T9	1
valid_sources[0x67]	4564	1			T1	12		T9	1		T10	10
valid_sources[0x68]	4644	1			T1	8		T2	1		T9	1
valid_sources[0x69]	3195	1			T1	6		T9	1		T10	11
valid_sources[0x6a]	6394	1			T1	10		T9	4		T10	10
valid_sources[0x6b]	3176	1			T1	15		T9	2		T10	7
valid_sources[0x6c]	3911	1			T1	3		T4	155		T8	5
valid_sources[0x6d]	4303	1			T1	8		T4	154		T9	1
valid_sources[0x6e]	3733	1			T1	4		T10	19		T11	12
valid_sources[0x6f]	3431	1			T1	8		T2	3		T9	1
valid_sources[0x70]	3009	1			T1	17		T9	10		T10	18
valid_sources[0x71]	4317	1			T1	15		T2	4		T9	2
valid_sources[0x72]	3877	1			T1	29		T2	6		T9	1
valid_sources[0x73]	3540	1			T1	9		T2	5		T3	4
valid_sources[0x74]	3799	1			T1	25		T2	1		T10	14
valid_sources[0x75]	3332	1			T1	19		T2	3		T3	5
valid_sources[0x76]	3079	1			T1	3		T10	9		T22	5
valid_sources[0x77]	3323	1			T1	14		T3	17		T9	1
valid_sources[0x78]	6279	1			T1	5		T9	1		T10	14
valid_sources[0x79]	3862	1			T1	18		T3	2		T9	4
valid_sources[0x7a]	7417	1			T1	8		T2	17		T4	9
valid_sources[0x7b]	3556	1			T1	15		T4	112		T8	7
valid_sources[0x7c]	4419	1			T1	11		T9	8		T10	18
valid_sources[0x7d]	3815	1			T1	20		T3	11		T8	4
valid_sources[0x7e]	3546	1			T1	6		T9	1		T10	10
valid_sources[0x7f]	3771	1			T1	12		T4	366		T10	13
valid_sources[0x80]	3715	1			T1	14		T10	17		T22	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

258011

1

T1

687

T2

51

T3

86

values[0x0]

all_enables

biggest_size

83693

1

T1

262

T2

15

T3

28

values[0x1]

all_enables

biggest_size

44546

1

T1

146

T2

8

T3

15