Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13563105	14561	0	0
gen_assertions[0].RstEnOn_A	13563105	1133	0	0
gen_assertions[0].RstNOff_A	13563105	14561	0	0
gen_assertions[0].RstNOn_A	13563105	1133	0	0
gen_assertions[1].RstEnOff_A	54252190	13209	0	0
gen_assertions[1].RstEnOn_A	54252190	1086	0	0
gen_assertions[1].RstNOff_A	54252190	13209	0	0
gen_assertions[1].RstNOn_A	54252190	1086	0	0
gen_assertions[2].RstEnOff_A	27127034	13287	0	0
gen_assertions[2].RstEnOn_A	27127034	1102	0	0
gen_assertions[2].RstNOff_A	27127034	13287	0	0
gen_assertions[2].RstNOn_A	27127034	1102	0	0
gen_assertions[3].RstEnOff_A	27127064	13316	0	0
gen_assertions[3].RstEnOn_A	27127064	1106	0	0
gen_assertions[3].RstNOff_A	27127064	13316	0	0
gen_assertions[3].RstNOn_A	27127064	1106	0	0
gen_assertions[4].RstEnOff_A	1712751	22445	0	0
gen_assertions[4].RstEnOn_A	1712751	1168	0	0
gen_assertions[4].RstNOff_A	1712751	22445	0	0
gen_assertions[4].RstNOn_A	1712751	1168	0	0
gen_assertions[5].RstEnOff_A	13563105	14824	0	0
gen_assertions[5].RstEnOn_A	13563105	1212	0	0
gen_assertions[5].RstNOff_A	13563105	14824	0	0
gen_assertions[5].RstNOn_A	13563105	1212	0	0
gen_assertions[6].RstEnOff_A	13563105	14849	0	0
gen_assertions[6].RstEnOn_A	13563105	1239	0	0
gen_assertions[6].RstNOff_A	13563105	14849	0	0
gen_assertions[6].RstNOn_A	13563105	1239	0	0
gen_assertions[7].RstEnOff_A	13563105	14913	0	0
gen_assertions[7].RstEnOn_A	13563105	1309	0	0
gen_assertions[7].RstNOff_A	13563105	14913	0	0
gen_assertions[7].RstNOn_A	13563105	1309	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14561	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	37	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	4	0	0
T8	3549	4	0	0
T9	2792	4	0	0
T10	45052	75	0	0
T22	0	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1133	0	0
T3	3616	9	0	0
T4	39645	3	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	4	0	0
T8	3549	0	0	0
T9	2792	0	0	0
T10	45052	0	0	0
T12	5892	0	0	0
T22	7149	2	0	0
T23	0	1	0	0
T34	0	1	0	0
T63	0	5	0	0
T66	0	5	0	0
T67	0	6	0	0
T68	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14561	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	37	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	4	0	0
T8	3549	4	0	0
T9	2792	4	0	0
T10	45052	75	0	0
T22	0	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1133	0	0
T3	3616	9	0	0
T4	39645	3	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	4	0	0
T8	3549	0	0	0
T9	2792	0	0	0
T10	45052	0	0	0
T12	5892	0	0	0
T22	7149	2	0	0
T23	0	1	0	0
T34	0	1	0	0
T63	0	5	0	0
T66	0	5	0	0
T67	0	6	0	0
T68	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54252190	13209	0	0
T1	117003	72	0	0
T2	13627	4	0	0
T3	14472	15	0	0
T4	158546	29	0	0
T5	19819	0	0	0
T6	14819	3	0	0
T7	34075	7	0	0
T8	14198	4	0	0
T9	11175	3	0	0
T10	180223	69	0	0
T22	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54252190	1086	0	0
T3	14472	7	0	0
T4	158546	4	0	0
T5	19819	0	0	0
T6	14819	0	0	0
T7	34075	7	0	0
T8	14198	0	0	0
T9	11175	1	0	0
T10	180223	0	0	0
T12	23579	0	0	0
T22	28599	4	0	0
T47	0	7	0	0
T66	0	3	0	0
T67	0	8	0	0
T68	0	6	0	0
T69	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54252190	13209	0	0
T1	117003	72	0	0
T2	13627	4	0	0
T3	14472	15	0	0
T4	158546	29	0	0
T5	19819	0	0	0
T6	14819	3	0	0
T7	34075	7	0	0
T8	14198	4	0	0
T9	11175	3	0	0
T10	180223	69	0	0
T22	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54252190	1086	0	0
T3	14472	7	0	0
T4	158546	4	0	0
T5	19819	0	0	0
T6	14819	0	0	0
T7	34075	7	0	0
T8	14198	0	0	0
T9	11175	1	0	0
T10	180223	0	0	0
T12	23579	0	0	0
T22	28599	4	0	0
T47	0	7	0	0
T66	0	3	0	0
T67	0	8	0	0
T68	0	6	0	0
T69	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127034	13287	0	0
T1	58488	72	0	0
T2	6814	4	0	0
T3	7235	15	0	0
T4	79285	29	0	0
T5	9909	0	0	0
T6	7407	3	0	0
T7	17037	8	0	0
T8	7098	4	0	0
T9	5588	2	0	0
T10	90121	69	0	0
T22	0	5	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127034	1102	0	0
T3	7235	1	0	0
T4	79285	4	0	0
T5	9909	0	0	0
T6	7407	0	0	0
T7	17037	8	0	0
T8	7098	0	0	0
T9	5588	0	0	0
T10	90121	0	0	0
T12	11785	0	0	0
T22	14299	5	0	0
T34	0	1	0	0
T47	0	10	0	0
T67	0	7	0	0
T68	0	6	0	0
T70	0	10	0	0
T71	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127034	13287	0	0
T1	58488	72	0	0
T2	6814	4	0	0
T3	7235	15	0	0
T4	79285	29	0	0
T5	9909	0	0	0
T6	7407	3	0	0
T7	17037	8	0	0
T8	7098	4	0	0
T9	5588	2	0	0
T10	90121	69	0	0
T22	0	5	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127034	1102	0	0
T3	7235	1	0	0
T4	79285	4	0	0
T5	9909	0	0	0
T6	7407	0	0	0
T7	17037	8	0	0
T8	7098	0	0	0
T9	5588	0	0	0
T10	90121	0	0	0
T12	11785	0	0	0
T22	14299	5	0	0
T34	0	1	0	0
T47	0	10	0	0
T67	0	7	0	0
T68	0	6	0	0
T70	0	10	0	0
T71	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127064	13316	0	0
T1	58494	72	0	0
T2	6814	4	0	0
T3	7234	15	0	0
T4	79281	29	0	0
T5	9909	0	0	0
T6	7406	3	0	0
T7	17037	9	0	0
T8	7098	4	0	0
T9	5585	2	0	0
T10	90107	69	0	0
T22	0	6	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127064	1106	0	0
T4	79281	4	0	0
T5	9909	0	0	0
T6	7406	0	0	0
T7	17037	9	0	0
T8	7098	0	0	0
T9	5585	0	0	0
T10	90107	0	0	0
T11	58373	0	0	0
T12	11781	0	0	0
T22	14299	6	0	0
T47	0	10	0	0
T67	0	7	0	0
T68	0	9	0	0
T70	0	12	0	0
T71	0	6	0	0
T72	0	22	0	0
T73	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127064	13316	0	0
T1	58494	72	0	0
T2	6814	4	0	0
T3	7234	15	0	0
T4	79281	29	0	0
T5	9909	0	0	0
T6	7406	3	0	0
T7	17037	9	0	0
T8	7098	4	0	0
T9	5585	2	0	0
T10	90107	69	0	0
T22	0	6	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127064	1106	0	0
T4	79281	4	0	0
T5	9909	0	0	0
T6	7406	0	0	0
T7	17037	9	0	0
T8	7098	0	0	0
T9	5585	0	0	0
T10	90107	0	0	0
T11	58373	0	0	0
T12	11781	0	0	0
T22	14299	6	0	0
T47	0	10	0	0
T67	0	7	0	0
T68	0	9	0	0
T70	0	12	0	0
T71	0	6	0	0
T72	0	22	0	0
T73	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	22445	0	0
T1	3671	75	0	0
T2	425	6	0	0
T3	451	17	0	0
T4	5044	58	0	0
T5	618	2	0	0
T6	461	6	0	0
T7	1064	10	0	0
T8	442	6	0	0
T9	348	6	0	0
T10	5646	93	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	1168	0	0
T4	5044	3	0	0
T5	618	0	0	0
T6	461	0	0	0
T7	1064	9	0	0
T8	442	0	0	0
T9	348	0	0	0
T10	5646	0	0	0
T11	3663	0	0	0
T12	737	0	0	0
T22	892	7	0	0
T34	0	1	0	0
T47	0	13	0	0
T67	0	9	0	0
T68	0	10	0	0
T70	0	13	0	0
T71	0	8	0	0
T74	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	22445	0	0
T1	3671	75	0	0
T2	425	6	0	0
T3	451	17	0	0
T4	5044	58	0	0
T5	618	2	0	0
T6	461	6	0	0
T7	1064	10	0	0
T8	442	6	0	0
T9	348	6	0	0
T10	5646	93	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	1168	0	0
T4	5044	3	0	0
T5	618	0	0	0
T6	461	0	0	0
T7	1064	9	0	0
T8	442	0	0	0
T9	348	0	0	0
T10	5646	0	0	0
T11	3663	0	0	0
T12	737	0	0	0
T22	892	7	0	0
T34	0	1	0	0
T47	0	13	0	0
T67	0	9	0	0
T68	0	10	0	0
T70	0	13	0	0
T71	0	8	0	0
T74	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14824	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	36	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	11	0	0
T8	3549	4	0	0
T9	2792	4	0	0
T10	45052	75	0	0
T22	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1212	0	0
T4	39645	2	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	11	0	0
T8	3549	0	0	0
T9	2792	0	0	0
T10	45052	0	0	0
T11	29190	0	0	0
T12	5892	0	0	0
T22	7149	9	0	0
T36	0	1	0	0
T47	0	11	0	0
T67	0	9	0	0
T68	0	10	0	0
T70	0	11	0	0
T71	0	8	0	0
T72	0	26	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14824	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	36	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	11	0	0
T8	3549	4	0	0
T9	2792	4	0	0
T10	45052	75	0	0
T22	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1212	0	0
T4	39645	2	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	11	0	0
T8	3549	0	0	0
T9	2792	0	0	0
T10	45052	0	0	0
T11	29190	0	0	0
T12	5892	0	0	0
T22	7149	9	0	0
T36	0	1	0	0
T47	0	11	0	0
T67	0	9	0	0
T68	0	10	0	0
T70	0	11	0	0
T71	0	8	0	0
T72	0	26	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14849	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	37	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	10	0	0
T8	3549	4	0	0
T9	2792	4	0	0
T10	45052	75	0	0
T22	0	10	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1239	0	0
T4	39645	3	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	10	0	0
T8	3549	0	0	0
T9	2792	0	0	0
T10	45052	0	0	0
T11	29190	0	0	0
T12	5892	0	0	0
T22	7149	10	0	0
T36	0	1	0	0
T47	0	14	0	0
T67	0	8	0	0
T68	0	8	0	0
T70	0	11	0	0
T71	0	9	0	0
T72	0	26	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14849	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	37	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	10	0	0
T8	3549	4	0	0
T9	2792	4	0	0
T10	45052	75	0	0
T22	0	10	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1239	0	0
T4	39645	3	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	10	0	0
T8	3549	0	0	0
T9	2792	0	0	0
T10	45052	0	0	0
T11	29190	0	0	0
T12	5892	0	0	0
T22	7149	10	0	0
T36	0	1	0	0
T47	0	14	0	0
T67	0	8	0	0
T68	0	8	0	0
T70	0	11	0	0
T71	0	9	0	0
T72	0	26	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14913	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	37	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	11	0	0
T8	3549	4	0	0
T9	2792	5	0	0
T10	45052	75	0	0
T22	0	10	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1309	0	0
T4	39645	3	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	11	0	0
T8	3549	0	0	0
T9	2792	1	0	0
T10	45052	0	0	0
T11	29190	0	0	0
T12	5892	0	0	0
T22	7149	10	0	0
T47	0	15	0	0
T67	0	10	0	0
T68	0	7	0	0
T70	0	14	0	0
T71	0	11	0	0
T72	0	21	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	14913	0	0
T1	29248	75	0	0
T2	3406	4	0	0
T3	3616	16	0	0
T4	39645	37	0	0
T5	4954	0	0	0
T6	3703	4	0	0
T7	8517	11	0	0
T8	3549	4	0	0
T9	2792	5	0	0
T10	45052	75	0	0
T22	0	10	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	1309	0	0
T4	39645	3	0	0
T5	4954	0	0	0
T6	3703	0	0	0
T7	8517	11	0	0
T8	3549	0	0	0
T9	2792	1	0	0
T10	45052	0	0	0
T11	29190	0	0	0
T12	5892	0	0	0
T22	7149	10	0	0
T47	0	15	0	0
T67	0	10	0	0
T68	0	7	0	0
T70	0	14	0	0
T71	0	11	0	0
T72	0	21	0	0