Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12823117	7747	0	0
alert_regwen_rd_A	12823117	5289	0	0
cpu_regwen_rd_A	12823117	5514	0	0
sw_rst_ctrl_n_0_rd_A	12823117	11450	0	0
sw_rst_ctrl_n_1_rd_A	12823117	11293	0	0
sw_rst_ctrl_n_2_rd_A	12823117	11268	0	0
sw_rst_ctrl_n_3_rd_A	12823117	11558	0	0
sw_rst_ctrl_n_4_rd_A	12823117	11326	0	0
sw_rst_ctrl_n_5_rd_A	12823117	10927	0	0
sw_rst_ctrl_n_6_rd_A	12823117	10989	0	0
sw_rst_ctrl_n_7_rd_A	12823117	11188	0	0
sw_rst_regwen_0_rd_A	12823117	5865	0	0
sw_rst_regwen_1_rd_A	12823117	6278	0	0
sw_rst_regwen_2_rd_A	12823117	5750	0	0
sw_rst_regwen_3_rd_A	12823117	5983	0	0
sw_rst_regwen_4_rd_A	12823117	6103	0	0
sw_rst_regwen_5_rd_A	12823117	6191	0	0
sw_rst_regwen_6_rd_A	12823117	5978	0	0
sw_rst_regwen_7_rd_A	12823117	5985	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	7747	0	0
T48	10411	3	0	0
T49	3312	18	0	0
T51	11794	1	0	0
T52	12214	384	0	0
T53	10107	637	0	0
T78	2596	6	0	0
T79	20882	3	0	0
T80	21464	3	0	0
T81	3700	74	0	0
T86	19328	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5289	0	0
T13	3536	0	0	0
T14	3671	0	0	0
T15	4942	0	0	0
T25	42023	0	0	0
T57	2035	0	0	0
T58	2045	0	0	0
T67	48006	76	0	0
T72	0	316	0	0
T88	0	54	0	0
T90	0	347	0	0
T92	0	81	0	0
T95	1661	0	0	0
T96	5074	0	0	0
T97	5091	0	0	0
T98	0	77	0	0
T99	0	209	0	0
T100	0	24	0	0
T101	0	58	0	0
T119	0	54	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5514	0	0
T13	3536	0	0	0
T14	3671	0	0	0
T15	4942	0	0	0
T25	42023	0	0	0
T57	2035	0	0	0
T58	2045	0	0	0
T67	48006	61	0	0
T72	0	327	0	0
T88	0	44	0	0
T90	0	368	0	0
T92	0	84	0	0
T95	1661	0	0	0
T96	5074	0	0	0
T97	5091	0	0	0
T98	0	77	0	0
T99	0	157	0	0
T100	0	40	0	0
T101	0	44	0	0
T119	0	29	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	11450	0	0
T23	4783	39	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	12	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	55	0	0
T64	5676	0	0	0
T67	0	197	0	0
T69	0	3	0	0
T70	0	216	0	0
T72	0	618	0	0
T73	0	216	0	0
T88	0	53	0	0
T120	0	24	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	11293	0	0
T23	4783	61	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	11	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	64	0	0
T64	5676	0	0	0
T67	0	152	0	0
T69	0	8	0	0
T70	0	216	0	0
T72	0	653	0	0
T73	0	198	0	0
T95	0	7	0	0
T120	0	18	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	11268	0	0
T23	4783	39	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	51	0	0
T64	5676	0	0	0
T67	0	197	0	0
T69	0	11	0	0
T70	0	235	0	0
T72	0	668	0	0
T73	0	226	0	0
T88	0	73	0	0
T95	0	2	0	0
T120	0	33	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	11558	0	0
T23	4783	25	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	2	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	37	0	0
T64	5676	0	0	0
T67	0	179	0	0
T69	0	10	0	0
T70	0	197	0	0
T72	0	705	0	0
T73	0	185	0	0
T95	0	2	0	0
T120	0	30	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	11326	0	0
T23	4783	46	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	5	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	70	0	0
T64	5676	0	0	0
T67	0	151	0	0
T69	0	4	0	0
T70	0	211	0	0
T72	0	647	0	0
T73	0	201	0	0
T95	0	3	0	0
T120	0	28	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	10927	0	0
T23	4783	39	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	4	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	42	0	0
T64	5676	0	0	0
T67	0	139	0	0
T69	0	11	0	0
T70	0	208	0	0
T72	0	612	0	0
T73	0	196	0	0
T95	0	5	0	0
T120	0	35	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	10989	0	0
T23	4783	33	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	13	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	52	0	0
T64	5676	0	0	0
T67	0	133	0	0
T70	0	200	0	0
T72	0	560	0	0
T73	0	215	0	0
T88	0	56	0	0
T95	0	5	0	0
T120	0	27	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	11188	0	0
T23	4783	59	0	0
T24	53288	0	0	0
T33	194593	0	0	0
T34	2464	0	0	0
T35	3147	0	0	0
T36	5159	11	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	61	0	0
T64	5676	0	0	0
T67	0	164	0	0
T69	0	4	0	0
T70	0	200	0	0
T72	0	667	0	0
T73	0	213	0	0
T95	0	8	0	0
T120	0	29	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5865	0	0
T24	53288	0	0	0
T36	5159	1	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	51	0	0
T69	0	4	0	0
T70	0	23	0	0
T72	0	352	0	0
T73	0	51	0	0
T88	0	45	0	0
T90	0	365	0	0
T92	0	62	0	0
T121	0	26	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	6278	0	0
T13	3536	0	0	0
T14	3671	0	0	0
T15	4942	0	0	0
T25	42023	0	0	0
T57	2035	0	0	0
T58	2045	0	0	0
T67	48006	54	0	0
T70	0	25	0	0
T72	0	391	0	0
T73	0	29	0	0
T88	0	38	0	0
T90	0	385	0	0
T92	0	80	0	0
T95	1661	0	0	0
T96	5074	0	0	0
T97	5091	0	0	0
T98	0	75	0	0
T119	0	25	0	0
T121	0	10	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5750	0	0
T24	53288	0	0	0
T36	5159	6	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	66	0	0
T69	0	3	0	0
T70	0	38	0	0
T72	0	341	0	0
T73	0	39	0	0
T88	0	44	0	0
T90	0	318	0	0
T92	0	78	0	0
T121	0	29	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5983	0	0
T24	53288	0	0	0
T36	5159	9	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	55	0	0
T69	0	7	0	0
T70	0	20	0	0
T72	0	326	0	0
T73	0	37	0	0
T88	0	42	0	0
T90	0	405	0	0
T92	0	65	0	0
T121	0	13	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	6103	0	0
T24	53288	0	0	0
T36	5159	9	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	53	0	0
T70	0	30	0	0
T72	0	319	0	0
T73	0	30	0	0
T88	0	59	0	0
T90	0	415	0	0
T92	0	73	0	0
T119	0	26	0	0
T121	0	17	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	6191	0	0
T24	53288	0	0	0
T36	5159	2	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	67	0	0
T69	0	9	0	0
T70	0	17	0	0
T72	0	344	0	0
T73	0	21	0	0
T88	0	42	0	0
T90	0	408	0	0
T92	0	71	0	0
T121	0	25	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5978	0	0
T24	53288	0	0	0
T36	5159	1	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	57	0	0
T69	0	2	0	0
T70	0	41	0	0
T72	0	335	0	0
T73	0	23	0	0
T88	0	40	0	0
T90	0	390	0	0
T92	0	34	0	0
T121	0	4	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12823117	5985	0	0
T24	53288	0	0	0
T36	5159	11	0	0
T56	1233	0	0	0
T59	5470	0	0	0
T62	2304	0	0	0
T63	4780	0	0	0
T64	5676	0	0	0
T65	2264	0	0	0
T66	2106	0	0	0
T67	48006	60	0	0
T69	0	1	0	0
T70	0	37	0	0
T72	0	358	0	0
T73	0	44	0	0
T88	0	47	0	0
T90	0	365	0	0
T92	0	56	0	0
T121	0	24	0	0