Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T9
1	0	Covered	T4,T67,T69

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56514619	8954	0	0
CascadeEffAonToRstPorAboveRise_A	56514619	8954	0	0
CascadeEffAonToRstPorIoAboveFall_A	54252190	8954	0	0
CascadeEffAonToRstPorIoAboveRise_A	54252190	8954	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27127034	8954	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27127034	8954	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13563105	8954	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13563105	8954	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27127064	8954	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27127064	8954	0	0
CascadeLcToLcAboveFall_A	56514619	22599	0	0
CascadeLcToLcAboveRise_A	56514619	22599	0	0
CascadeLcToLcAonAboveFall_A	1712751	22599	0	0
CascadeLcToLcAonAboveRise_A	1712751	22599	0	0
CascadeLcToLcShadowedAboveFall_A	56514619	22599	0	0
CascadeLcToLcShadowedAboveRise_A	56514619	22599	0	0
CascadePorToAonAboveFall_A	1712751	7082	0	0
CascadeSysToSysAboveFall_A	56514619	22599	0	0
CascadeSysToSysAboveRise_A	56514619	22599	0	0
ScanRstToAonRise_A	1712751	236	0	0
StablePorToAonRise_A	1712751	8954	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12018074	22599	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12018074	22599	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12018074	22599	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12018074	22599	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13563105	22599	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13563105	22599	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12018074	22599	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12018074	22599	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12018074	22599	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12018074	22599	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	8954	0	0
T1	121885	27	0	0
T2	14197	2	0	0
T3	15075	1	0	0
T4	165163	22	0	0
T5	20644	2	0	0
T6	15432	2	0	0
T7	35495	1	0	0
T8	14796	2	0	0
T9	11634	2	0	0
T10	187697	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	8954	0	0
T1	121885	27	0	0
T2	14197	2	0	0
T3	15075	1	0	0
T4	165163	22	0	0
T5	20644	2	0	0
T6	15432	2	0	0
T7	35495	1	0	0
T8	14796	2	0	0
T9	11634	2	0	0
T10	187697	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54252190	8954	0	0
T1	117003	27	0	0
T2	13627	2	0	0
T3	14472	1	0	0
T4	158546	22	0	0
T5	19819	2	0	0
T6	14819	2	0	0
T7	34075	1	0	0
T8	14198	2	0	0
T9	11175	2	0	0
T10	180223	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54252190	8954	0	0
T1	117003	27	0	0
T2	13627	2	0	0
T3	14472	1	0	0
T4	158546	22	0	0
T5	19819	2	0	0
T6	14819	2	0	0
T7	34075	1	0	0
T8	14198	2	0	0
T9	11175	2	0	0
T10	180223	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127034	8954	0	0
T1	58488	27	0	0
T2	6814	2	0	0
T3	7235	1	0	0
T4	79285	22	0	0
T5	9909	2	0	0
T6	7407	2	0	0
T7	17037	1	0	0
T8	7098	2	0	0
T9	5588	2	0	0
T10	90121	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127034	8954	0	0
T1	58488	27	0	0
T2	6814	2	0	0
T3	7235	1	0	0
T4	79285	22	0	0
T5	9909	2	0	0
T6	7407	2	0	0
T7	17037	1	0	0
T8	7098	2	0	0
T9	5588	2	0	0
T10	90121	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	8954	0	0
T1	29248	27	0	0
T2	3406	2	0	0
T3	3616	1	0	0
T4	39645	22	0	0
T5	4954	2	0	0
T6	3703	2	0	0
T7	8517	1	0	0
T8	3549	2	0	0
T9	2792	2	0	0
T10	45052	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	8954	0	0
T1	29248	27	0	0
T2	3406	2	0	0
T3	3616	1	0	0
T4	39645	22	0	0
T5	4954	2	0	0
T6	3703	2	0	0
T7	8517	1	0	0
T8	3549	2	0	0
T9	2792	2	0	0
T10	45052	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127064	8954	0	0
T1	58494	27	0	0
T2	6814	2	0	0
T3	7234	1	0	0
T4	79281	22	0	0
T5	9909	2	0	0
T6	7406	2	0	0
T7	17037	1	0	0
T8	7098	2	0	0
T9	5585	2	0	0
T10	90107	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27127064	8954	0	0
T1	58494	27	0	0
T2	6814	2	0	0
T3	7234	1	0	0
T4	79281	22	0	0
T5	9909	2	0	0
T6	7406	2	0	0
T7	17037	1	0	0
T8	7098	2	0	0
T9	5585	2	0	0
T10	90107	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	22599	0	0
T1	121885	102	0	0
T2	14197	6	0	0
T3	15075	17	0	0
T4	165163	56	0	0
T5	20644	2	0	0
T6	15432	6	0	0
T7	35495	1	0	0
T8	14796	6	0	0
T9	11634	6	0	0
T10	187697	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	22599	0	0
T1	121885	102	0	0
T2	14197	6	0	0
T3	15075	17	0	0
T4	165163	56	0	0
T5	20644	2	0	0
T6	15432	6	0	0
T7	35495	1	0	0
T8	14796	6	0	0
T9	11634	6	0	0
T10	187697	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	22599	0	0
T1	3671	102	0	0
T2	425	6	0	0
T3	451	17	0	0
T4	5044	56	0	0
T5	618	2	0	0
T6	461	6	0	0
T7	1064	1	0	0
T8	442	6	0	0
T9	348	6	0	0
T10	5646	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	22599	0	0
T1	3671	102	0	0
T2	425	6	0	0
T3	451	17	0	0
T4	5044	56	0	0
T5	618	2	0	0
T6	461	6	0	0
T7	1064	1	0	0
T8	442	6	0	0
T9	348	6	0	0
T10	5646	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	22599	0	0
T1	121885	102	0	0
T2	14197	6	0	0
T3	15075	17	0	0
T4	165163	56	0	0
T5	20644	2	0	0
T6	15432	6	0	0
T7	35495	1	0	0
T8	14796	6	0	0
T9	11634	6	0	0
T10	187697	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	22599	0	0
T1	121885	102	0	0
T2	14197	6	0	0
T3	15075	17	0	0
T4	165163	56	0	0
T5	20644	2	0	0
T6	15432	6	0	0
T7	35495	1	0	0
T8	14796	6	0	0
T9	11634	6	0	0
T10	187697	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	7082	0	0
T1	3671	27	0	0
T2	425	1	0	0
T3	451	1	0	0
T4	5044	11	0	0
T5	618	17	0	0
T6	461	1	0	0
T7	1064	1	0	0
T8	442	1	0	0
T9	348	1	0	0
T10	5646	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	22599	0	0
T1	121885	102	0	0
T2	14197	6	0	0
T3	15075	17	0	0
T4	165163	56	0	0
T5	20644	2	0	0
T6	15432	6	0	0
T7	35495	1	0	0
T8	14796	6	0	0
T9	11634	6	0	0
T10	187697	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56514619	22599	0	0
T1	121885	102	0	0
T2	14197	6	0	0
T3	15075	17	0	0
T4	165163	56	0	0
T5	20644	2	0	0
T6	15432	6	0	0
T7	35495	1	0	0
T8	14796	6	0	0
T9	11634	6	0	0
T10	187697	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	236	0	0
T24	7095	0	0	0
T36	673	1	0	0
T56	161	0	0	0
T59	729	0	0	0
T62	323	0	0	0
T63	721	0	0	0
T64	731	0	0	0
T65	312	0	0	0
T66	351	0	0	0
T67	6707	3	0	0
T72	0	4	0	0
T88	0	1	0	0
T89	0	7	0	0
T90	0	7	0	0
T91	0	3	0	0
T99	0	1	0	0
T100	0	1	0	0
T119	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712751	8954	0	0
T1	3671	27	0	0
T2	425	2	0	0
T3	451	1	0	0
T4	5044	22	0	0
T5	618	2	0	0
T6	461	2	0	0
T7	1064	1	0	0
T8	442	2	0	0
T9	348	2	0	0
T10	5646	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	22599	0	0
T1	29248	102	0	0
T2	3406	6	0	0
T3	3616	17	0	0
T4	39645	56	0	0
T5	4954	2	0	0
T6	3703	6	0	0
T7	8517	1	0	0
T8	3549	6	0	0
T9	2792	6	0	0
T10	45052	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13563105	22599	0	0
T1	29248	102	0	0
T2	3406	6	0	0
T3	3616	17	0	0
T4	39645	56	0	0
T5	4954	2	0	0
T6	3703	6	0	0
T7	8517	1	0	0
T8	3549	6	0	0
T9	2792	6	0	0
T10	45052	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12018074	22599	0	0
T1	25980	102	0	0
T2	3070	6	0	0
T3	2492	17	0	0
T4	34912	56	0	0
T5	4839	2	0	0
T6	3414	6	0	0
T7	8451	1	0	0
T8	3212	6	0	0
T9	2456	6	0	0
T10	41849	102	0	0