Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	591636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

356135

1

T1

4

T2

387

T4

1044

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	504771	1			T2	539		T4	1522		T5	1442
values[0x0]	220853	1			T1	10		T2	253		T4	610
values[0x1]	222147	1			T1	8		T2	240		T4	570

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	496564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

451207

1

T1

5

T2

485

T4

1318

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6109	1			T2	3		T5	6		T9	2
valid_sources[0x01]	4489	1			T2	6		T5	16		T9	1
valid_sources[0x02]	2709	1			T2	6		T5	17		T9	2
valid_sources[0x03]	2749	1			T1	1		T2	2		T5	7
valid_sources[0x04]	3782	1			T2	6		T5	4		T6	1
valid_sources[0x05]	4219	1			T2	2		T5	9		T24	450
valid_sources[0x06]	2806	1			T2	2		T5	15		T34	80
valid_sources[0x07]	6710	1			T2	8		T5	7		T6	4
valid_sources[0x08]	3444	1			T1	2		T2	4		T5	8
valid_sources[0x09]	4433	1			T2	4		T5	14		T6	3
valid_sources[0x0a]	3399	1			T2	2		T4	247		T5	17
valid_sources[0x0b]	3885	1			T2	2		T5	13		T10	2
valid_sources[0x0c]	3601	1			T2	2		T5	20		T9	4
valid_sources[0x0d]	3228	1			T2	8		T5	5		T9	1
valid_sources[0x0e]	3037	1			T2	7		T5	5		T6	1
valid_sources[0x0f]	3323	1			T2	2		T5	10		T23	13
valid_sources[0x10]	2754	1			T2	5		T5	6		T6	2
valid_sources[0x11]	4780	1			T2	3		T5	3		T6	2
valid_sources[0x12]	7959	1			T1	1		T2	5		T4	2
valid_sources[0x13]	3543	1			T2	4		T5	8		T10	4
valid_sources[0x14]	3038	1			T2	3		T5	17		T9	2
valid_sources[0x15]	3744	1			T2	6		T5	9		T9	1
valid_sources[0x16]	3175	1			T2	6		T5	16		T6	3
valid_sources[0x17]	3257	1			T2	8		T4	58		T5	10
valid_sources[0x18]	3270	1			T2	4		T5	13		T6	1
valid_sources[0x19]	3505	1			T2	4		T5	9		T6	8
valid_sources[0x1a]	3154	1			T2	1		T5	1		T6	2
valid_sources[0x1b]	4189	1			T2	3		T5	12		T10	5
valid_sources[0x1c]	3138	1			T2	7		T5	5		T9	1
valid_sources[0x1d]	3548	1			T2	1		T5	13		T6	1
valid_sources[0x1e]	3480	1			T2	7		T5	8		T9	6
valid_sources[0x1f]	3072	1			T2	3		T4	99		T5	4
valid_sources[0x20]	3248	1			T2	2		T4	113		T5	13
valid_sources[0x21]	2939	1			T2	4		T5	8		T6	2
valid_sources[0x22]	4031	1			T2	5		T5	7		T10	1
valid_sources[0x23]	3216	1			T2	5		T4	108		T5	9
valid_sources[0x24]	3567	1			T2	3		T5	10		T6	5
valid_sources[0x25]	3142	1			T2	5		T5	6		T9	3
valid_sources[0x26]	3198	1			T2	3		T5	16		T6	4
valid_sources[0x27]	3777	1			T1	1		T2	12		T5	21
valid_sources[0x28]	2853	1			T2	8		T5	5		T6	1
valid_sources[0x29]	3678	1			T2	1		T5	9		T6	4
valid_sources[0x2a]	3160	1			T2	6		T5	10		T6	3
valid_sources[0x2b]	3172	1			T2	3		T5	7		T10	1
valid_sources[0x2c]	3208	1			T1	1		T2	3		T5	4
valid_sources[0x2d]	3132	1			T2	2		T5	11		T23	8
valid_sources[0x2e]	3386	1			T2	2		T5	8		T6	5
valid_sources[0x2f]	3184	1			T2	4		T4	577		T9	2
valid_sources[0x30]	3398	1			T2	4		T5	6		T6	3
valid_sources[0x31]	3474	1			T2	1		T5	14		T6	1
valid_sources[0x32]	3230	1			T2	8		T5	15		T6	4
valid_sources[0x33]	3147	1			T2	8		T5	6		T9	4
valid_sources[0x34]	2965	1			T2	5		T5	13		T21	14
valid_sources[0x35]	3263	1			T2	1		T5	10		T34	72
valid_sources[0x36]	3168	1			T2	3		T5	9		T6	3
valid_sources[0x37]	2752	1			T2	4		T5	14		T6	2
valid_sources[0x38]	3298	1			T2	3		T5	9		T6	4
valid_sources[0x39]	3426	1			T2	1		T5	10		T6	1
valid_sources[0x3a]	2915	1			T2	3		T5	13		T9	4
valid_sources[0x3b]	3394	1			T2	4		T5	6		T6	1
valid_sources[0x3c]	4092	1			T2	9		T5	16		T6	1
valid_sources[0x3d]	3112	1			T2	2		T5	4		T6	3
valid_sources[0x3e]	3197	1			T2	2		T5	9		T6	3
valid_sources[0x3f]	3340	1			T2	6		T5	11		T6	4
valid_sources[0x40]	3388	1			T2	7		T5	11		T6	2
valid_sources[0x41]	3261	1			T2	4		T5	6		T9	3
valid_sources[0x42]	2710	1			T2	3		T5	8		T10	1
valid_sources[0x43]	3435	1			T2	2		T5	13		T9	1
valid_sources[0x44]	2697	1			T2	4		T5	7		T6	1
valid_sources[0x45]	3189	1			T2	1		T5	6		T6	2
valid_sources[0x46]	3438	1			T5	13		T9	1		T34	69
valid_sources[0x47]	2956	1			T2	5		T5	13		T6	2
valid_sources[0x48]	3146	1			T2	3		T5	10		T6	1
valid_sources[0x49]	2918	1			T2	2		T5	9		T6	10
valid_sources[0x4a]	3220	1			T2	3		T5	11		T6	4
valid_sources[0x4b]	3340	1			T2	3		T5	7		T9	7
valid_sources[0x4c]	4870	1			T2	5		T4	10		T6	2
valid_sources[0x4d]	3415	1			T2	7		T5	17		T34	63
valid_sources[0x4e]	3442	1			T2	3		T5	9		T34	75
valid_sources[0x4f]	3203	1			T1	2		T2	4		T5	15
valid_sources[0x50]	3218	1			T2	2		T5	13		T21	8
valid_sources[0x51]	3406	1			T5	13		T9	4		T34	83
valid_sources[0x52]	5223	1			T2	5		T5	8		T10	1
valid_sources[0x53]	3117	1			T2	3		T5	5		T6	1
valid_sources[0x54]	4466	1			T2	5		T5	16		T10	1
valid_sources[0x55]	3695	1			T2	6		T4	190		T5	7
valid_sources[0x56]	3690	1			T2	5		T5	4		T21	3
valid_sources[0x57]	3257	1			T2	4		T5	15		T6	1
valid_sources[0x58]	3121	1			T1	2		T2	6		T5	8
valid_sources[0x59]	6770	1			T2	4		T5	3		T6	4
valid_sources[0x5a]	3179	1			T2	6		T5	10		T9	1
valid_sources[0x5b]	3212	1			T2	3		T5	17		T6	4
valid_sources[0x5c]	8811	1			T2	6		T5	6		T6	4
valid_sources[0x5d]	3823	1			T2	1		T5	7		T6	1
valid_sources[0x5e]	3785	1			T4	2		T5	9		T6	2
valid_sources[0x5f]	3225	1			T2	4		T5	2		T6	1
valid_sources[0x60]	2617	1			T2	2		T5	5		T9	13
valid_sources[0x61]	3826	1			T2	5		T5	8		T34	81
valid_sources[0x62]	3340	1			T2	10		T5	10		T10	1
valid_sources[0x63]	3938	1			T2	8		T5	14		T6	5
valid_sources[0x64]	2888	1			T2	3		T5	10		T6	5
valid_sources[0x65]	3500	1			T4	1		T5	5		T6	3
valid_sources[0x66]	6197	1			T2	4		T5	8		T9	1
valid_sources[0x67]	3608	1			T2	5		T5	6		T10	1
valid_sources[0x68]	3637	1			T2	1		T5	7		T6	6
valid_sources[0x69]	3235	1			T2	3		T5	9		T6	6
valid_sources[0x6a]	5091	1			T2	3		T5	27		T21	2
valid_sources[0x6b]	2796	1			T2	6		T5	2		T9	2
valid_sources[0x6c]	3150	1			T2	4		T4	2		T5	15
valid_sources[0x6d]	3454	1			T5	21		T9	2		T34	88
valid_sources[0x6e]	3147	1			T2	6		T5	8		T34	82
valid_sources[0x6f]	3878	1			T2	6		T5	12		T6	2
valid_sources[0x70]	6214	1			T2	5		T5	7		T10	3
valid_sources[0x71]	3451	1			T2	4		T5	13		T9	1
valid_sources[0x72]	2566	1			T2	5		T5	9		T9	1
valid_sources[0x73]	3285	1			T2	6		T5	6		T10	1
valid_sources[0x74]	3257	1			T2	1		T5	5		T9	1
valid_sources[0x75]	4286	1			T2	5		T5	8		T10	2
valid_sources[0x76]	3585	1			T2	4		T5	7		T10	1
valid_sources[0x77]	3200	1			T2	4		T4	2		T5	8
valid_sources[0x78]	3046	1			T2	2		T5	12		T6	1
valid_sources[0x79]	3150	1			T2	3		T4	113		T5	13
valid_sources[0x7a]	7084	1			T2	3		T5	18		T9	1
valid_sources[0x7b]	4208	1			T2	5		T5	10		T6	1
valid_sources[0x7c]	3217	1			T2	7		T5	16		T6	2
valid_sources[0x7d]	4505	1			T2	5		T5	9		T6	1
valid_sources[0x7e]	3555	1			T2	4		T5	15		T9	5
valid_sources[0x7f]	3594	1			T2	10		T5	15		T6	4
valid_sources[0x80]	3980	1			T2	7		T5	11		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237254

1

T2

270

T4

705

T5

651

values[0x0]

all_enables

biggest_size

77400

1

T1

2

T2

86

T4

231

values[0x1]

all_enables

biggest_size

41481

1

T1

2

T2

31

T4

108