Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T12
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T9
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T21
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T21,T24
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T21,T24
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T21
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T21,T24
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T21,T24
1	0	Covered	T3,T4,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12555342	13499	0	0
gen_assertions[0].RstEnOn_A	12555342	995	0	0
gen_assertions[0].RstNOff_A	12555342	13499	0	0
gen_assertions[0].RstNOn_A	12555342	995	0	0
gen_assertions[1].RstEnOff_A	50220987	12313	0	0
gen_assertions[1].RstEnOn_A	50220987	990	0	0
gen_assertions[1].RstNOff_A	50220987	12313	0	0
gen_assertions[1].RstNOn_A	50220987	990	0	0
gen_assertions[2].RstEnOff_A	25111085	12329	0	0
gen_assertions[2].RstEnOn_A	25111085	956	0	0
gen_assertions[2].RstNOff_A	25111085	12329	0	0
gen_assertions[2].RstNOn_A	25111085	956	0	0
gen_assertions[3].RstEnOff_A	25111291	12413	0	0
gen_assertions[3].RstEnOn_A	25111291	1036	0	0
gen_assertions[3].RstNOff_A	25111291	12413	0	0
gen_assertions[3].RstNOn_A	25111291	1036	0	0
gen_assertions[4].RstEnOff_A	1584645	21079	0	0
gen_assertions[4].RstEnOn_A	1584645	1091	0	0
gen_assertions[4].RstNOff_A	1584645	21079	0	0
gen_assertions[4].RstNOn_A	1584645	1091	0	0
gen_assertions[5].RstEnOff_A	12555342	13703	0	0
gen_assertions[5].RstEnOn_A	12555342	1074	0	0
gen_assertions[5].RstNOff_A	12555342	13703	0	0
gen_assertions[5].RstNOn_A	12555342	1074	0	0
gen_assertions[6].RstEnOff_A	12555342	13793	0	0
gen_assertions[6].RstEnOn_A	12555342	1169	0	0
gen_assertions[6].RstNOff_A	12555342	13793	0	0
gen_assertions[6].RstNOn_A	12555342	1169	0	0
gen_assertions[7].RstEnOff_A	12555342	13826	0	0
gen_assertions[7].RstEnOn_A	12555342	1199	0	0
gen_assertions[7].RstNOff_A	12555342	13826	0	0
gen_assertions[7].RstNOn_A	12555342	1199	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13499	0	0
T2	11056	4	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	4	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	6	0	0
T22	0	75	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	995	0	0
T2	11056	4	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	0	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	6	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T12	0	1	0	0
T21	0	6	0	0
T24	0	10	0	0
T34	0	10	0	0
T38	0	1	0	0
T54	0	27	0	0
T55	0	2	0	0
T56	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13499	0	0
T2	11056	4	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	4	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	6	0	0
T22	0	75	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	995	0	0
T2	11056	4	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	0	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	6	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T12	0	1	0	0
T21	0	6	0	0
T24	0	10	0	0
T34	0	10	0	0
T38	0	1	0	0
T54	0	27	0	0
T55	0	2	0	0
T56	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50220987	12313	0	0
T2	44227	7	0	0
T3	23335	0	0	0
T4	173672	33	0	0
T5	128000	25	0	0
T6	21668	5	0	0
T7	11968	0	0	0
T8	9886	0	0	0
T9	14768	17	0	0
T10	9947	4	0	0
T11	10951	0	0	0
T12	0	2	0	0
T13	0	4	0	0
T21	0	8	0	0
T22	0	64	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50220987	990	0	0
T2	44227	7	0	0
T3	23335	0	0	0
T4	173672	0	0	0
T5	128000	0	0	0
T6	21668	1	0	0
T7	11968	0	0	0
T8	9886	0	0	0
T9	14768	4	0	0
T10	9947	0	0	0
T11	10951	0	0	0
T21	0	8	0	0
T24	0	14	0	0
T34	0	6	0	0
T54	0	29	0	0
T59	0	1	0	0
T63	0	4	0	0
T85	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50220987	12313	0	0
T2	44227	7	0	0
T3	23335	0	0	0
T4	173672	33	0	0
T5	128000	25	0	0
T6	21668	5	0	0
T7	11968	0	0	0
T8	9886	0	0	0
T9	14768	17	0	0
T10	9947	4	0	0
T11	10951	0	0	0
T12	0	2	0	0
T13	0	4	0	0
T21	0	8	0	0
T22	0	64	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50220987	990	0	0
T2	44227	7	0	0
T3	23335	0	0	0
T4	173672	0	0	0
T5	128000	0	0	0
T6	21668	1	0	0
T7	11968	0	0	0
T8	9886	0	0	0
T9	14768	4	0	0
T10	9947	0	0	0
T11	10951	0	0	0
T21	0	8	0	0
T24	0	14	0	0
T34	0	6	0	0
T54	0	29	0	0
T59	0	1	0	0
T63	0	4	0	0
T85	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111085	12329	0	0
T2	22114	10	0	0
T3	11662	0	0	0
T4	86844	33	0	0
T5	64002	25	0	0
T6	10834	4	0	0
T7	5985	0	0	0
T8	4943	0	0	0
T9	7383	17	0	0
T10	4972	4	0	0
T11	5476	0	0	0
T12	0	2	0	0
T13	0	4	0	0
T21	0	9	0	0
T22	0	64	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111085	956	0	0
T2	22114	10	0	0
T3	11662	0	0	0
T4	86844	0	0	0
T5	64002	0	0	0
T6	10834	0	0	0
T7	5985	0	0	0
T8	4943	0	0	0
T9	7383	1	0	0
T10	4972	0	0	0
T11	5476	0	0	0
T21	0	9	0	0
T24	0	12	0	0
T34	0	7	0	0
T38	0	1	0	0
T54	0	28	0	0
T63	0	7	0	0
T85	0	6	0	0
T86	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111085	12329	0	0
T2	22114	10	0	0
T3	11662	0	0	0
T4	86844	33	0	0
T5	64002	25	0	0
T6	10834	4	0	0
T7	5985	0	0	0
T8	4943	0	0	0
T9	7383	17	0	0
T10	4972	4	0	0
T11	5476	0	0	0
T12	0	2	0	0
T13	0	4	0	0
T21	0	9	0	0
T22	0	64	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111085	956	0	0
T2	22114	10	0	0
T3	11662	0	0	0
T4	86844	0	0	0
T5	64002	0	0	0
T6	10834	0	0	0
T7	5985	0	0	0
T8	4943	0	0	0
T9	7383	1	0	0
T10	4972	0	0	0
T11	5476	0	0	0
T21	0	9	0	0
T24	0	12	0	0
T34	0	7	0	0
T38	0	1	0	0
T54	0	28	0	0
T63	0	7	0	0
T85	0	6	0	0
T86	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111291	12413	0	0
T2	22114	8	0	0
T3	11670	0	0	0
T4	86850	33	0	0
T5	63999	25	0	0
T6	10834	4	0	0
T7	5984	0	0	0
T8	4943	0	0	0
T9	7382	17	0	0
T10	4972	4	0	0
T11	5476	0	0	0
T12	0	2	0	0
T13	0	4	0	0
T21	0	10	0	0
T22	0	64	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111291	1036	0	0
T2	22114	8	0	0
T3	11670	0	0	0
T4	86850	0	0	0
T5	63999	0	0	0
T6	10834	0	0	0
T7	5984	0	0	0
T8	4943	0	0	0
T9	7382	0	0	0
T10	4972	0	0	0
T11	5476	0	0	0
T21	0	10	0	0
T24	0	16	0	0
T34	0	9	0	0
T54	0	30	0	0
T63	0	5	0	0
T85	0	5	0	0
T87	0	36	0	0
T88	0	1	0	0
T89	0	39	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111291	12413	0	0
T2	22114	8	0	0
T3	11670	0	0	0
T4	86850	33	0	0
T5	63999	25	0	0
T6	10834	4	0	0
T7	5984	0	0	0
T8	4943	0	0	0
T9	7382	17	0	0
T10	4972	4	0	0
T11	5476	0	0	0
T12	0	2	0	0
T13	0	4	0	0
T21	0	10	0	0
T22	0	64	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111291	1036	0	0
T2	22114	8	0	0
T3	11670	0	0	0
T4	86850	0	0	0
T5	63999	0	0	0
T6	10834	0	0	0
T7	5984	0	0	0
T8	4943	0	0	0
T9	7382	0	0	0
T10	4972	0	0	0
T11	5476	0	0	0
T21	0	10	0	0
T24	0	16	0	0
T34	0	9	0	0
T54	0	30	0	0
T63	0	5	0	0
T85	0	5	0	0
T87	0	36	0	0
T88	0	1	0	0
T89	0	39	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	21079	0	0
T1	228	1	0	0
T2	1380	9	0	0
T3	730	2	0	0
T4	5496	53	0	0
T5	4039	47	0	0
T6	675	6	0	0
T7	373	2	0	0
T8	307	2	0	0
T9	460	18	0	0
T10	311	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	1091	0	0
T2	1380	8	0	0
T3	730	0	0	0
T4	5496	0	0	0
T5	4039	0	0	0
T6	675	0	0	0
T7	373	0	0	0
T8	307	0	0	0
T9	460	0	0	0
T10	311	0	0	0
T11	340	0	0	0
T21	0	12	0	0
T24	0	9	0	0
T34	0	9	0	0
T54	0	29	0	0
T63	0	7	0	0
T85	0	8	0	0
T86	0	1	0	0
T87	0	31	0	0
T89	0	33	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	21079	0	0
T1	228	1	0	0
T2	1380	9	0	0
T3	730	2	0	0
T4	5496	53	0	0
T5	4039	47	0	0
T6	675	6	0	0
T7	373	2	0	0
T8	307	2	0	0
T9	460	18	0	0
T10	311	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	1091	0	0
T2	1380	8	0	0
T3	730	0	0	0
T4	5496	0	0	0
T5	4039	0	0	0
T6	675	0	0	0
T7	373	0	0	0
T8	307	0	0	0
T9	460	0	0	0
T10	311	0	0	0
T11	340	0	0	0
T21	0	12	0	0
T24	0	9	0	0
T34	0	9	0	0
T54	0	29	0	0
T63	0	7	0	0
T85	0	8	0	0
T86	0	1	0	0
T87	0	31	0	0
T89	0	33	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13703	0	0
T2	11056	10	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	5	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	11	0	0
T22	0	75	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	1074	0	0
T2	11056	10	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	1	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	0	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T21	0	11	0	0
T24	0	12	0	0
T34	0	8	0	0
T54	0	23	0	0
T63	0	9	0	0
T85	0	9	0	0
T86	0	1	0	0
T87	0	38	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13703	0	0
T2	11056	10	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	5	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	11	0	0
T22	0	75	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	1074	0	0
T2	11056	10	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	1	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	0	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T21	0	11	0	0
T24	0	12	0	0
T34	0	8	0	0
T54	0	23	0	0
T63	0	9	0	0
T85	0	9	0	0
T86	0	1	0	0
T87	0	38	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13793	0	0
T2	11056	13	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	4	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	13	0	0
T22	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	1169	0	0
T2	11056	13	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	0	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	0	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T21	0	13	0	0
T24	0	13	0	0
T34	0	7	0	0
T54	0	25	0	0
T63	0	10	0	0
T85	0	10	0	0
T87	0	36	0	0
T89	0	38	0	0
T90	0	9	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13793	0	0
T2	11056	13	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	4	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	13	0	0
T22	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	1169	0	0
T2	11056	13	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	0	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	0	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T21	0	13	0	0
T24	0	13	0	0
T34	0	7	0	0
T54	0	25	0	0
T63	0	10	0	0
T85	0	10	0	0
T87	0	36	0	0
T89	0	38	0	0
T90	0	9	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13826	0	0
T2	11056	11	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	4	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	16	0	0
T22	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	1199	0	0
T2	11056	11	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	0	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	0	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T21	0	16	0	0
T24	0	10	0	0
T34	0	8	0	0
T54	0	29	0	0
T63	0	10	0	0
T85	0	9	0	0
T86	0	1	0	0
T87	0	34	0	0
T89	0	41	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	13826	0	0
T2	11056	11	0	0
T3	5832	0	0	0
T4	43424	34	0	0
T5	32007	27	0	0
T6	5416	4	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	17	0	0
T10	2486	4	0	0
T11	2736	0	0	0
T12	0	3	0	0
T13	0	4	0	0
T21	0	16	0	0
T22	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	1199	0	0
T2	11056	11	0	0
T3	5832	0	0	0
T4	43424	0	0	0
T5	32007	0	0	0
T6	5416	0	0	0
T7	2991	0	0	0
T8	2471	0	0	0
T9	3691	0	0	0
T10	2486	0	0	0
T11	2736	0	0	0
T21	0	16	0	0
T24	0	10	0	0
T34	0	8	0	0
T54	0	29	0	0
T63	0	10	0	0
T85	0	9	0	0
T86	0	1	0	0
T87	0	34	0	0
T89	0	41	0	0