Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11956431	10036	0	0
alert_regwen_rd_A	11956431	5261	0	0
cpu_regwen_rd_A	11956431	4792	0	0
sw_rst_ctrl_n_0_rd_A	11956431	10062	0	0
sw_rst_ctrl_n_1_rd_A	11956431	9872	0	0
sw_rst_ctrl_n_2_rd_A	11956431	9820	0	0
sw_rst_ctrl_n_3_rd_A	11956431	9965	0	0
sw_rst_ctrl_n_4_rd_A	11956431	10233	0	0
sw_rst_ctrl_n_5_rd_A	11956431	10210	0	0
sw_rst_ctrl_n_6_rd_A	11956431	9815	0	0
sw_rst_ctrl_n_7_rd_A	11956431	9985	0	0
sw_rst_regwen_0_rd_A	11956431	5622	0	0
sw_rst_regwen_1_rd_A	11956431	5684	0	0
sw_rst_regwen_2_rd_A	11956431	5515	0	0
sw_rst_regwen_3_rd_A	11956431	5363	0	0
sw_rst_regwen_4_rd_A	11956431	5637	0	0
sw_rst_regwen_5_rd_A	11956431	5512	0	0
sw_rst_regwen_6_rd_A	11956431	5580	0	0
sw_rst_regwen_7_rd_A	11956431	5486	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	10036	0	0
T64	19791	5	0	0
T65	9967	632	0	0
T66	8956	2	0	0
T67	4225	23	0	0
T68	7013	246	0	0
T92	20210	2	0	0
T93	4277	420	0	0
T94	2626	4	0	0
T95	12318	376	0	0
T96	14893	420	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5261	0	0
T4	38944	92	0	0
T5	27290	0	0	0
T6	5178	0	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	2243	0	0	0
T13	2218	0	0	0
T99	0	63	0	0
T101	0	47	0	0
T104	0	330	0	0
T106	0	45	0	0
T122	0	105	0	0
T123	0	16	0	0
T124	0	19	0	0
T125	0	211	0	0
T126	0	50	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	4792	0	0
T4	38944	65	0	0
T5	27290	0	0	0
T6	5178	0	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	2243	0	0	0
T13	2218	0	0	0
T99	0	57	0	0
T101	0	53	0	0
T104	0	318	0	0
T106	0	35	0	0
T122	0	111	0	0
T123	0	41	0	0
T124	0	24	0	0
T125	0	205	0	0
T126	0	37	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	10062	0	0
T2	11014	124	0	0
T3	5478	0	0	0
T4	38944	70	0	0
T5	27290	0	0	0
T6	5178	5	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	5	0	0
T38	0	13	0	0
T85	0	131	0	0
T88	0	7	0	0
T99	0	76	0	0
T101	0	63	0	0
T127	0	11	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	9872	0	0
T2	11014	64	0	0
T3	5478	0	0	0
T4	38944	69	0	0
T5	27290	0	0	0
T6	5178	8	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	5	0	0
T38	0	13	0	0
T85	0	117	0	0
T88	0	3	0	0
T99	0	66	0	0
T101	0	73	0	0
T127	0	10	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	9820	0	0
T2	11014	115	0	0
T3	5478	0	0	0
T4	38944	51	0	0
T5	27290	0	0	0
T6	5178	6	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	7	0	0
T38	0	7	0	0
T85	0	80	0	0
T88	0	13	0	0
T99	0	67	0	0
T101	0	35	0	0
T127	0	9	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	9965	0	0
T2	11014	149	0	0
T3	5478	0	0	0
T4	38944	69	0	0
T5	27290	0	0	0
T6	5178	0	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	7	0	0
T38	0	14	0	0
T85	0	81	0	0
T88	0	10	0	0
T99	0	60	0	0
T101	0	45	0	0
T104	0	642	0	0
T128	0	14	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	10233	0	0
T2	11014	121	0	0
T3	5478	0	0	0
T4	38944	70	0	0
T5	27290	0	0	0
T6	5178	16	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	10	0	0
T38	0	7	0	0
T85	0	81	0	0
T88	0	6	0	0
T99	0	64	0	0
T101	0	82	0	0
T127	0	11	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	10210	0	0
T2	11014	140	0	0
T3	5478	0	0	0
T4	38944	83	0	0
T5	27290	0	0	0
T6	5178	17	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	17	0	0
T38	0	9	0	0
T85	0	91	0	0
T99	0	94	0	0
T101	0	65	0	0
T127	0	2	0	0
T128	0	20	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	9815	0	0
T2	11014	142	0	0
T3	5478	0	0	0
T4	38944	59	0	0
T5	27290	0	0	0
T6	5178	7	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	13	0	0
T38	0	16	0	0
T85	0	82	0	0
T88	0	7	0	0
T99	0	88	0	0
T101	0	68	0	0
T127	0	16	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	9985	0	0
T2	11014	125	0	0
T3	5478	0	0	0
T4	38944	45	0	0
T5	27290	0	0	0
T6	5178	2	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T12	0	5	0	0
T38	0	7	0	0
T85	0	103	0	0
T88	0	8	0	0
T99	0	60	0	0
T101	0	35	0	0
T127	0	6	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5622	0	0
T2	11014	42	0	0
T3	5478	0	0	0
T4	38944	54	0	0
T5	27290	0	0	0
T6	5178	4	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	9	0	0
T85	0	9	0	0
T99	0	50	0	0
T101	0	56	0	0
T104	0	283	0	0
T128	0	2	0	0
T129	0	4	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5684	0	0
T2	11014	15	0	0
T3	5478	0	0	0
T4	38944	60	0	0
T5	27290	0	0	0
T6	5178	2	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	2	0	0
T85	0	22	0	0
T99	0	91	0	0
T101	0	47	0	0
T104	0	330	0	0
T128	0	6	0	0
T129	0	6	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5515	0	0
T2	11014	14	0	0
T3	5478	0	0	0
T4	38944	77	0	0
T5	27290	0	0	0
T6	5178	12	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	6	0	0
T85	0	15	0	0
T99	0	90	0	0
T101	0	61	0	0
T104	0	364	0	0
T127	0	12	0	0
T128	0	6	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5363	0	0
T2	11014	10	0	0
T3	5478	0	0	0
T4	38944	70	0	0
T5	27290	0	0	0
T6	5178	2	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	7	0	0
T85	0	27	0	0
T88	0	7	0	0
T99	0	77	0	0
T101	0	50	0	0
T104	0	316	0	0
T128	0	8	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5637	0	0
T2	11014	13	0	0
T3	5478	0	0	0
T4	38944	74	0	0
T5	27290	0	0	0
T6	5178	0	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	8	0	0
T85	0	10	0	0
T88	0	10	0	0
T99	0	64	0	0
T101	0	48	0	0
T104	0	354	0	0
T127	0	13	0	0
T128	0	9	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5512	0	0
T2	11014	14	0	0
T3	5478	0	0	0
T4	38944	89	0	0
T5	27290	0	0	0
T6	5178	9	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	9	0	0
T85	0	28	0	0
T88	0	7	0	0
T99	0	81	0	0
T101	0	59	0	0
T104	0	340	0	0
T128	0	10	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5580	0	0
T2	11014	19	0	0
T3	5478	0	0	0
T4	38944	65	0	0
T5	27290	0	0	0
T6	5178	5	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	5	0	0
T85	0	12	0	0
T99	0	71	0	0
T101	0	55	0	0
T104	0	309	0	0
T127	0	2	0	0
T128	0	7	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11956431	5486	0	0
T2	11014	9	0	0
T3	5478	0	0	0
T4	38944	79	0	0
T5	27290	0	0	0
T6	5178	2	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	0	0	0
T10	2245	0	0	0
T11	2647	0	0	0
T38	0	1	0	0
T85	0	39	0	0
T88	0	8	0	0
T99	0	79	0	0
T101	0	31	0	0
T104	0	299	0	0
T128	0	13	0	0