Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11167474	12663	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11167474	116798	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11167474	6416538	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11167474	186590	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11167474	12663	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11167474	116798	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11167474	6416538	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11167474	186590	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	12663	0	0
T4	38944	34	0	0
T5	27290	27	0	0
T6	5178	4	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	17	0	0
T10	2245	4	0	0
T11	2647	0	0	0
T12	2243	3	0	0
T13	2218	4	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	153	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	116798	0	0
T4	38944	307	0	0
T5	27290	243	0	0
T6	5178	37	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	153	0	0
T10	2245	37	0	0
T11	2647	0	0	0
T12	2243	27	0	0
T13	2218	38	0	0
T22	0	718	0	0
T23	0	37	0	0
T24	0	1380	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	6416538	0	0
T1	1752	1172	0	0
T2	11014	10389	0	0
T3	5478	562	0	0
T4	38944	29124	0	0
T5	27290	18916	0	0
T6	5178	4227	0	0
T7	2901	619	0	0
T8	2356	733	0	0
T9	2460	1638	0	0
T10	2245	1269	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	186590	0	0
T4	38944	512	0	0
T5	27290	398	0	0
T6	5178	69	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	250	0	0
T10	2245	56	0	0
T11	2647	0	0	0
T12	2243	46	0	0
T13	2218	65	0	0
T22	0	1108	0	0
T23	0	63	0	0
T24	0	2230	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	12663	0	0
T4	38944	34	0	0
T5	27290	27	0	0
T6	5178	4	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	17	0	0
T10	2245	4	0	0
T11	2647	0	0	0
T12	2243	3	0	0
T13	2218	4	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	153	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	116798	0	0
T4	38944	307	0	0
T5	27290	243	0	0
T6	5178	37	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	153	0	0
T10	2245	37	0	0
T11	2647	0	0	0
T12	2243	27	0	0
T13	2218	38	0	0
T22	0	718	0	0
T23	0	37	0	0
T24	0	1380	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	6416538	0	0
T1	1752	1172	0	0
T2	11014	10389	0	0
T3	5478	562	0	0
T4	38944	29124	0	0
T5	27290	18916	0	0
T6	5178	4227	0	0
T7	2901	619	0	0
T8	2356	733	0	0
T9	2460	1638	0	0
T10	2245	1269	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	186590	0	0
T4	38944	512	0	0
T5	27290	398	0	0
T6	5178	69	0	0
T7	2901	0	0	0
T8	2356	0	0	0
T9	2460	250	0	0
T10	2245	56	0	0
T11	2647	0	0	0
T12	2243	46	0	0
T13	2218	65	0	0
T22	0	1108	0	0
T23	0	63	0	0
T24	0	2230	0	0