Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T13
1	0	Covered	T5,T6,T24

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52314873	8676	0	0
CascadeEffAonToRstPorAboveRise_A	52314873	8676	0	0
CascadeEffAonToRstPorIoAboveFall_A	50220987	8676	0	0
CascadeEffAonToRstPorIoAboveRise_A	50220987	8676	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25111085	8676	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25111085	8676	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12555342	8676	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12555342	8676	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25111291	8676	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25111291	8676	0	0
CascadeLcToLcAboveFall_A	52314873	21339	0	0
CascadeLcToLcAboveRise_A	52314873	21339	0	0
CascadeLcToLcAonAboveFall_A	1584645	21339	0	0
CascadeLcToLcAonAboveRise_A	1584645	21339	0	0
CascadeLcToLcShadowedAboveFall_A	52314873	21339	0	0
CascadeLcToLcShadowedAboveRise_A	52314873	21339	0	0
CascadePorToAonAboveFall_A	1584645	6915	0	0
CascadeSysToSysAboveFall_A	52314873	21339	0	0
CascadeSysToSysAboveRise_A	52314873	21339	0	0
ScanRstToAonRise_A	1584645	208	0	0
StablePorToAonRise_A	1584645	8676	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11167474	21339	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11167474	21339	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11167474	21339	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11167474	21339	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12555342	21339	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12555342	21339	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11167474	21339	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11167474	21339	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11167474	21339	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11167474	21339	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	8676	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	19	0	0
T5	133356	20	0	0
T6	22574	2	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	1	0	0
T10	10363	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	8676	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	19	0	0
T5	133356	20	0	0
T6	22574	2	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	1	0	0
T10	10363	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50220987	8676	0	0
T1	7373	1	0	0
T2	44227	1	0	0
T3	23335	8	0	0
T4	173672	19	0	0
T5	128000	20	0	0
T6	21668	2	0	0
T7	11968	2	0	0
T8	9886	2	0	0
T9	14768	1	0	0
T10	9947	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50220987	8676	0	0
T1	7373	1	0	0
T2	44227	1	0	0
T3	23335	8	0	0
T4	173672	19	0	0
T5	128000	20	0	0
T6	21668	2	0	0
T7	11968	2	0	0
T8	9886	2	0	0
T9	14768	1	0	0
T10	9947	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111085	8676	0	0
T1	3686	1	0	0
T2	22114	1	0	0
T3	11662	8	0	0
T4	86844	19	0	0
T5	64002	20	0	0
T6	10834	2	0	0
T7	5985	2	0	0
T8	4943	2	0	0
T9	7383	1	0	0
T10	4972	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111085	8676	0	0
T1	3686	1	0	0
T2	22114	1	0	0
T3	11662	8	0	0
T4	86844	19	0	0
T5	64002	20	0	0
T6	10834	2	0	0
T7	5985	2	0	0
T8	4943	2	0	0
T9	7383	1	0	0
T10	4972	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	8676	0	0
T1	1842	1	0	0
T2	11056	1	0	0
T3	5832	8	0	0
T4	43424	19	0	0
T5	32007	20	0	0
T6	5416	2	0	0
T7	2991	2	0	0
T8	2471	2	0	0
T9	3691	1	0	0
T10	2486	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	8676	0	0
T1	1842	1	0	0
T2	11056	1	0	0
T3	5832	8	0	0
T4	43424	19	0	0
T5	32007	20	0	0
T6	5416	2	0	0
T7	2991	2	0	0
T8	2471	2	0	0
T9	3691	1	0	0
T10	2486	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111291	8676	0	0
T1	3686	1	0	0
T2	22114	1	0	0
T3	11670	8	0	0
T4	86850	19	0	0
T5	63999	20	0	0
T6	10834	2	0	0
T7	5984	2	0	0
T8	4943	2	0	0
T9	7382	1	0	0
T10	4972	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25111291	8676	0	0
T1	3686	1	0	0
T2	22114	1	0	0
T3	11670	8	0	0
T4	86850	19	0	0
T5	63999	20	0	0
T6	10834	2	0	0
T7	5984	2	0	0
T8	4943	2	0	0
T9	7382	1	0	0
T10	4972	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	21339	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	53	0	0
T5	133356	47	0	0
T6	22574	6	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	18	0	0
T10	10363	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	21339	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	53	0	0
T5	133356	47	0	0
T6	22574	6	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	18	0	0
T10	10363	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	21339	0	0
T1	228	1	0	0
T2	1380	1	0	0
T3	730	8	0	0
T4	5496	53	0	0
T5	4039	47	0	0
T6	675	6	0	0
T7	373	2	0	0
T8	307	2	0	0
T9	460	18	0	0
T10	311	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	21339	0	0
T1	228	1	0	0
T2	1380	1	0	0
T3	730	8	0	0
T4	5496	53	0	0
T5	4039	47	0	0
T6	675	6	0	0
T7	373	2	0	0
T8	307	2	0	0
T9	460	18	0	0
T10	311	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	21339	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	53	0	0
T5	133356	47	0	0
T6	22574	6	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	18	0	0
T10	10363	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	21339	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	53	0	0
T5	133356	47	0	0
T6	22574	6	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	18	0	0
T10	10363	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	6915	0	0
T1	228	1	0	0
T2	1380	1	0	0
T3	730	8	0	0
T4	5496	13	0	0
T5	4039	8	0	0
T6	675	1	0	0
T7	373	8	0	0
T8	307	5	0	0
T9	460	1	0	0
T10	311	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	21339	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	53	0	0
T5	133356	47	0	0
T6	22574	6	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	18	0	0
T10	10363	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52314873	21339	0	0
T1	7680	1	0	0
T2	46071	1	0	0
T3	24307	8	0	0
T4	180945	53	0	0
T5	133356	47	0	0
T6	22574	6	0	0
T7	12467	2	0	0
T8	10298	2	0	0
T9	15384	18	0	0
T10	10363	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	208	0	0
T4	5496	2	0	0
T5	4039	1	0	0
T6	675	0	0	0
T7	373	0	0	0
T8	307	0	0	0
T9	460	0	0	0
T10	311	0	0	0
T11	340	0	0	0
T12	299	0	0	0
T13	293	1	0	0
T34	0	9	0	0
T37	0	2	0	0
T54	0	3	0	0
T87	0	1	0	0
T89	0	4	0	0
T99	0	1	0	0
T107	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584645	8676	0	0
T1	228	1	0	0
T2	1380	1	0	0
T3	730	8	0	0
T4	5496	19	0	0
T5	4039	20	0	0
T6	675	2	0	0
T7	373	2	0	0
T8	307	2	0	0
T9	460	1	0	0
T10	311	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	21339	0	0
T1	1842	1	0	0
T2	11056	1	0	0
T3	5832	8	0	0
T4	43424	53	0	0
T5	32007	47	0	0
T6	5416	6	0	0
T7	2991	2	0	0
T8	2471	2	0	0
T9	3691	18	0	0
T10	2486	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12555342	21339	0	0
T1	1842	1	0	0
T2	11056	1	0	0
T3	5832	8	0	0
T4	43424	53	0	0
T5	32007	47	0	0
T6	5416	6	0	0
T7	2991	2	0	0
T8	2471	2	0	0
T9	3691	18	0	0
T10	2486	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11167474	21339	0	0
T1	1752	1	0	0
T2	11014	1	0	0
T3	5478	8	0	0
T4	38944	53	0	0
T5	27290	47	0	0
T6	5178	6	0	0
T7	2901	2	0	0
T8	2356	2	0	0
T9	2460	18	0	0
T10	2245	6	0	0