Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	664923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

401197

1

T1

3179

T2

142

T3

79

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	570856	1			T1	4666		T2	186		T3	99
values[0x0]	247262	1			T1	1972		T2	91		T3	64
values[0x1]	248002	1			T1	1894		T2	102		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	557558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

508562

1

T1

3996

T2

187

T3

98

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4233	1			T2	3		T4	4		T6	7
valid_sources[0x01]	4525	1			T4	10		T6	6		T7	2
valid_sources[0x02]	3526	1			T4	10		T6	2		T7	2
valid_sources[0x03]	3785	1			T2	1		T4	9		T6	4
valid_sources[0x04]	4560	1			T1	70		T4	7		T6	3
valid_sources[0x05]	4618	1			T1	236		T4	11		T6	3
valid_sources[0x06]	4191	1			T2	1		T4	5		T6	4
valid_sources[0x07]	3761	1			T4	11		T6	4		T8	1
valid_sources[0x08]	4484	1			T4	10		T6	3		T8	1
valid_sources[0x09]	3695	1			T4	16		T6	5		T8	3
valid_sources[0x0a]	4634	1			T1	112		T2	3		T4	6
valid_sources[0x0b]	3260	1			T4	5		T6	4		T7	1
valid_sources[0x0c]	3955	1			T1	8		T4	7		T6	5
valid_sources[0x0d]	3367	1			T1	2		T2	3		T4	6
valid_sources[0x0e]	3865	1			T4	4		T6	6		T8	2
valid_sources[0x0f]	3679	1			T2	2		T4	5		T6	6
valid_sources[0x10]	3890	1			T4	16		T6	7		T71	2
valid_sources[0x11]	5666	1			T1	1451		T4	8		T6	4
valid_sources[0x12]	4438	1			T2	2		T4	9		T6	6
valid_sources[0x13]	3479	1			T1	13		T4	6		T6	3
valid_sources[0x14]	3477	1			T4	2		T6	5		T7	1
valid_sources[0x15]	4173	1			T1	105		T2	1		T4	8
valid_sources[0x16]	7419	1			T2	1		T4	10		T6	3
valid_sources[0x17]	3588	1			T1	6		T4	8		T6	3
valid_sources[0x18]	4223	1			T4	12		T6	2		T7	2
valid_sources[0x19]	4166	1			T4	14		T6	6		T7	1
valid_sources[0x1a]	4082	1			T4	11		T6	2		T7	1
valid_sources[0x1b]	4375	1			T2	3		T4	5		T6	5
valid_sources[0x1c]	3619	1			T2	2		T4	14		T6	4
valid_sources[0x1d]	3420	1			T2	4		T4	1		T6	11
valid_sources[0x1e]	3397	1			T1	112		T4	12		T6	5
valid_sources[0x1f]	3143	1			T4	11		T6	5		T7	2
valid_sources[0x20]	4803	1			T4	9		T6	3		T7	1
valid_sources[0x21]	4928	1			T2	2		T4	2		T6	3
valid_sources[0x22]	5281	1			T4	9		T6	4		T8	2
valid_sources[0x23]	3362	1			T2	3		T4	10		T6	2
valid_sources[0x24]	3270	1			T4	12		T6	1		T7	1
valid_sources[0x25]	5016	1			T4	15		T6	2		T8	3
valid_sources[0x26]	3827	1			T1	112		T2	13		T4	10
valid_sources[0x27]	4350	1			T1	70		T4	12		T6	1
valid_sources[0x28]	5287	1			T2	8		T4	10		T6	2
valid_sources[0x29]	4168	1			T4	19		T6	5		T7	1
valid_sources[0x2a]	3854	1			T4	18		T6	2		T71	2
valid_sources[0x2b]	3927	1			T2	4		T4	6		T6	5
valid_sources[0x2c]	3514	1			T4	16		T6	4		T7	2
valid_sources[0x2d]	4725	1			T1	8		T2	3		T4	3
valid_sources[0x2e]	3260	1			T4	16		T7	1		T8	1
valid_sources[0x2f]	4134	1			T4	4		T6	2		T7	3
valid_sources[0x30]	3979	1			T1	156		T4	5		T6	5
valid_sources[0x31]	3826	1			T4	11		T6	8		T8	1
valid_sources[0x32]	4472	1			T4	8		T6	7		T8	2
valid_sources[0x33]	4706	1			T1	59		T2	1		T4	6
valid_sources[0x34]	4983	1			T2	9		T4	7		T6	6
valid_sources[0x35]	5608	1			T1	381		T2	15		T4	9
valid_sources[0x36]	3582	1			T1	203		T4	12		T6	3
valid_sources[0x37]	4136	1			T4	7		T6	5		T7	1
valid_sources[0x38]	3777	1			T4	7		T6	2		T11	4
valid_sources[0x39]	3457	1			T1	13		T4	1		T6	2
valid_sources[0x3a]	4637	1			T2	7		T4	3		T6	6
valid_sources[0x3b]	3850	1			T2	1		T4	9		T6	3
valid_sources[0x3c]	3875	1			T1	70		T2	1		T4	6
valid_sources[0x3d]	4220	1			T4	9		T6	1		T7	1
valid_sources[0x3e]	3901	1			T2	1		T4	7		T6	2
valid_sources[0x3f]	3038	1			T4	12		T6	5		T7	2
valid_sources[0x40]	3647	1			T2	2		T4	16		T6	2
valid_sources[0x41]	3534	1			T1	58		T4	19		T6	2
valid_sources[0x42]	3747	1			T4	14		T6	3		T7	1
valid_sources[0x43]	4588	1			T2	2		T4	4		T6	2
valid_sources[0x44]	5692	1			T1	204		T4	6		T6	5
valid_sources[0x45]	5090	1			T1	58		T4	11		T6	5
valid_sources[0x46]	4875	1			T1	2		T4	6		T6	5
valid_sources[0x47]	4649	1			T2	6		T4	13		T6	8
valid_sources[0x48]	3683	1			T2	2		T4	2		T6	6
valid_sources[0x49]	3104	1			T1	10		T4	8		T6	5
valid_sources[0x4a]	4075	1			T4	10		T6	6		T8	1
valid_sources[0x4b]	3345	1			T2	1		T4	15		T6	6
valid_sources[0x4c]	4866	1			T4	10		T6	4		T56	1
valid_sources[0x4d]	4273	1			T4	7		T6	1		T7	2
valid_sources[0x4e]	3951	1			T4	6		T6	2		T7	1
valid_sources[0x4f]	4288	1			T4	12		T6	3		T8	1
valid_sources[0x50]	8297	1			T4	11		T6	4		T7	2
valid_sources[0x51]	3324	1			T4	4		T6	3		T71	4
valid_sources[0x52]	3324	1			T4	14		T6	4		T7	2
valid_sources[0x53]	4187	1			T2	1		T4	12		T6	4
valid_sources[0x54]	3643	1			T4	4		T6	1		T7	2
valid_sources[0x55]	5161	1			T4	13		T6	7		T8	1
valid_sources[0x56]	4459	1			T1	5		T2	10		T4	6
valid_sources[0x57]	5141	1			T4	13		T6	8		T7	1
valid_sources[0x58]	3746	1			T4	11		T6	4		T7	1
valid_sources[0x59]	3702	1			T4	8		T6	4		T7	1
valid_sources[0x5a]	3462	1			T1	12		T4	7		T6	2
valid_sources[0x5b]	5308	1			T2	4		T4	14		T6	6
valid_sources[0x5c]	3656	1			T4	4		T6	5		T7	1
valid_sources[0x5d]	4642	1			T1	189		T4	12		T6	7
valid_sources[0x5e]	4263	1			T4	12		T6	2		T7	1
valid_sources[0x5f]	3803	1			T4	14		T6	3		T7	2
valid_sources[0x60]	4651	1			T4	4		T6	4		T7	1
valid_sources[0x61]	4481	1			T1	147		T2	7		T4	7
valid_sources[0x62]	4298	1			T4	6		T6	2		T8	2
valid_sources[0x63]	3492	1			T2	3		T4	9		T6	3
valid_sources[0x64]	8176	1			T4	17		T6	5		T7	1
valid_sources[0x65]	3404	1			T4	8		T6	1		T7	2
valid_sources[0x66]	4636	1			T4	4		T6	1		T7	1
valid_sources[0x67]	3278	1			T2	16		T4	22		T6	6
valid_sources[0x68]	4190	1			T4	19		T6	4		T7	2
valid_sources[0x69]	3174	1			T1	2		T2	3		T4	6
valid_sources[0x6a]	3239	1			T2	3		T4	4		T6	6
valid_sources[0x6b]	5659	1			T1	1663		T4	12		T6	5
valid_sources[0x6c]	3722	1			T1	143		T4	5		T6	3
valid_sources[0x6d]	3960	1			T4	10		T6	1		T7	1
valid_sources[0x6e]	3765	1			T4	8		T6	5		T7	2
valid_sources[0x6f]	3506	1			T4	21		T6	3		T8	3
valid_sources[0x70]	3273	1			T2	7		T4	6		T6	3
valid_sources[0x71]	3812	1			T2	1		T4	7		T6	5
valid_sources[0x72]	4419	1			T2	3		T4	7		T6	2
valid_sources[0x73]	3652	1			T2	3		T4	4		T6	5
valid_sources[0x74]	3945	1			T4	7		T6	2		T8	2
valid_sources[0x75]	3581	1			T2	2		T4	17		T6	8
valid_sources[0x76]	3325	1			T2	7		T4	6		T6	1
valid_sources[0x77]	4003	1			T4	7		T6	2		T7	1
valid_sources[0x78]	4428	1			T4	21		T6	2		T7	1
valid_sources[0x79]	3547	1			T1	7		T4	16		T6	3
valid_sources[0x7a]	3655	1			T4	5		T6	3		T8	1
valid_sources[0x7b]	3825	1			T2	4		T4	7		T6	2
valid_sources[0x7c]	3587	1			T4	6		T6	2		T7	1
valid_sources[0x7d]	3897	1			T2	1		T4	11		T6	3
valid_sources[0x7e]	5417	1			T4	5		T6	3		T7	1
valid_sources[0x7f]	5401	1			T2	22		T4	6		T6	5
valid_sources[0x80]	3923	1			T4	5		T6	8		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

268114

1

T1

2217

T2

87

T3

48

values[0x0]

all_enables

biggest_size

87009

1

T1

645

T2

36

T3

25

values[0x1]

all_enables

biggest_size

46074

1

T1

317

T2

19

T3

6