Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13298126	14913	0	0
gen_assertions[0].RstEnOn_A	13298126	1027	0	0
gen_assertions[0].RstNOff_A	13298126	14913	0	0
gen_assertions[0].RstNOn_A	13298126	1027	0	0
gen_assertions[1].RstEnOff_A	53192184	13535	0	0
gen_assertions[1].RstEnOn_A	53192184	1001	0	0
gen_assertions[1].RstNOff_A	53192184	13535	0	0
gen_assertions[1].RstNOn_A	53192184	1001	0	0
gen_assertions[2].RstEnOff_A	26597063	13577	0	0
gen_assertions[2].RstEnOn_A	26597063	981	0	0
gen_assertions[2].RstNOff_A	26597063	13577	0	0
gen_assertions[2].RstNOn_A	26597063	981	0	0
gen_assertions[3].RstEnOff_A	26597323	13638	0	0
gen_assertions[3].RstEnOn_A	26597323	1037	0	0
gen_assertions[3].RstNOff_A	26597323	13638	0	0
gen_assertions[3].RstNOn_A	26597323	1037	0	0
gen_assertions[4].RstEnOff_A	1680483	22689	0	0
gen_assertions[4].RstEnOn_A	1680483	1083	0	0
gen_assertions[4].RstNOff_A	1680483	22689	0	0
gen_assertions[4].RstNOn_A	1680483	1083	0	0
gen_assertions[5].RstEnOff_A	13298126	15175	0	0
gen_assertions[5].RstEnOn_A	13298126	1147	0	0
gen_assertions[5].RstNOff_A	13298126	15175	0	0
gen_assertions[5].RstNOn_A	13298126	1147	0	0
gen_assertions[6].RstEnOff_A	13298126	15236	0	0
gen_assertions[6].RstEnOn_A	13298126	1204	0	0
gen_assertions[6].RstNOff_A	13298126	15236	0	0
gen_assertions[6].RstNOn_A	13298126	1204	0	0
gen_assertions[7].RstEnOff_A	13298126	15267	0	0
gen_assertions[7].RstEnOn_A	13298126	1234	0	0
gen_assertions[7].RstNOff_A	13298126	15267	0	0
gen_assertions[7].RstNOn_A	13298126	1234	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	14913	0	0
T1	66701	112	0	0
T2	2990	4	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	7	0	0
T7	3460	4	0	0
T8	2761	4	0	0
T9	2679	5	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1027	0	0
T1	66701	26	0	0
T2	2990	0	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	7	0	0
T7	3460	0	0	0
T8	2761	0	0	0
T9	2679	1	0	0
T10	1565	0	0	0
T12	0	1	0	0
T36	0	1	0	0
T56	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T71	0	4	0	0
T72	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	14913	0	0
T1	66701	112	0	0
T2	2990	4	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	7	0	0
T7	3460	4	0	0
T8	2761	4	0	0
T9	2679	5	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1027	0	0
T1	66701	26	0	0
T2	2990	0	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	7	0	0
T7	3460	0	0	0
T8	2761	0	0	0
T9	2679	1	0	0
T10	1565	0	0	0
T12	0	1	0	0
T36	0	1	0	0
T56	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T71	0	4	0	0
T72	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53192184	13535	0	0
T1	266792	101	0	0
T2	11963	4	0	0
T3	15491	4	0	0
T4	125142	31	0	0
T5	14161	0	0	0
T6	12632	8	0	0
T7	13853	3	0	0
T8	11048	3	0	0
T9	10719	3	0	0
T10	6265	0	0	0
T11	0	4	0	0
T12	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53192184	1001	0	0
T1	266792	23	0	0
T2	11963	0	0	0
T3	15491	0	0	0
T4	125142	0	0	0
T5	14161	0	0	0
T6	12632	8	0	0
T7	13853	0	0	0
T8	11048	0	0	0
T9	10719	0	0	0
T10	6265	0	0	0
T36	0	2	0	0
T49	0	4	0	0
T52	0	4	0	0
T53	0	2	0	0
T56	0	2	0	0
T64	0	1	0	0
T71	0	7	0	0
T72	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53192184	13535	0	0
T1	266792	101	0	0
T2	11963	4	0	0
T3	15491	4	0	0
T4	125142	31	0	0
T5	14161	0	0	0
T6	12632	8	0	0
T7	13853	3	0	0
T8	11048	3	0	0
T9	10719	3	0	0
T10	6265	0	0	0
T11	0	4	0	0
T12	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53192184	1001	0	0
T1	266792	23	0	0
T2	11963	0	0	0
T3	15491	0	0	0
T4	125142	0	0	0
T5	14161	0	0	0
T6	12632	8	0	0
T7	13853	0	0	0
T8	11048	0	0	0
T9	10719	0	0	0
T10	6265	0	0	0
T36	0	2	0	0
T49	0	4	0	0
T52	0	4	0	0
T53	0	2	0	0
T56	0	2	0	0
T64	0	1	0	0
T71	0	7	0	0
T72	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597063	13577	0	0
T1	133401	105	0	0
T2	5982	5	0	0
T3	7745	4	0	0
T4	62590	31	0	0
T5	7080	0	0	0
T6	6315	8	0	0
T7	6926	3	0	0
T8	5524	3	0	0
T9	5357	4	0	0
T10	3132	0	0	0
T11	0	4	0	0
T12	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597063	981	0	0
T1	133401	27	0	0
T2	5982	1	0	0
T3	7745	0	0	0
T4	62590	0	0	0
T5	7080	0	0	0
T6	6315	8	0	0
T7	6926	0	0	0
T8	5524	0	0	0
T9	5357	1	0	0
T10	3132	0	0	0
T12	0	1	0	0
T36	0	2	0	0
T49	0	6	0	0
T56	0	1	0	0
T71	0	9	0	0
T72	0	5	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597063	13577	0	0
T1	133401	105	0	0
T2	5982	5	0	0
T3	7745	4	0	0
T4	62590	31	0	0
T5	7080	0	0	0
T6	6315	8	0	0
T7	6926	3	0	0
T8	5524	3	0	0
T9	5357	4	0	0
T10	3132	0	0	0
T11	0	4	0	0
T12	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597063	981	0	0
T1	133401	27	0	0
T2	5982	1	0	0
T3	7745	0	0	0
T4	62590	0	0	0
T5	7080	0	0	0
T6	6315	8	0	0
T7	6926	0	0	0
T8	5524	0	0	0
T9	5357	1	0	0
T10	3132	0	0	0
T12	0	1	0	0
T36	0	2	0	0
T49	0	6	0	0
T56	0	1	0	0
T71	0	9	0	0
T72	0	5	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597323	13638	0	0
T1	133403	98	0	0
T2	5983	5	0	0
T3	7744	4	0	0
T4	62584	31	0	0
T5	7080	0	0	0
T6	6315	9	0	0
T7	6925	3	0	0
T8	5524	3	0	0
T9	5359	4	0	0
T10	3132	0	0	0
T11	0	4	0	0
T12	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597323	1037	0	0
T1	133403	21	0	0
T2	5983	1	0	0
T3	7744	0	0	0
T4	62584	0	0	0
T5	7080	0	0	0
T6	6315	9	0	0
T7	6925	0	0	0
T8	5524	0	0	0
T9	5359	1	0	0
T10	3132	0	0	0
T36	0	3	0	0
T49	0	6	0	0
T52	0	6	0	0
T63	0	1	0	0
T71	0	9	0	0
T72	0	3	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597323	13638	0	0
T1	133403	98	0	0
T2	5983	5	0	0
T3	7744	4	0	0
T4	62584	31	0	0
T5	7080	0	0	0
T6	6315	9	0	0
T7	6925	3	0	0
T8	5524	3	0	0
T9	5359	4	0	0
T10	3132	0	0	0
T11	0	4	0	0
T12	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597323	1037	0	0
T1	133403	21	0	0
T2	5983	1	0	0
T3	7744	0	0	0
T4	62584	0	0	0
T5	7080	0	0	0
T6	6315	9	0	0
T7	6925	0	0	0
T8	5524	0	0	0
T9	5359	1	0	0
T10	3132	0	0	0
T36	0	3	0	0
T49	0	6	0	0
T52	0	6	0	0
T63	0	1	0	0
T71	0	9	0	0
T72	0	3	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	22689	0	0
T1	8477	164	0	0
T2	372	6	0	0
T3	482	6	0	0
T4	3974	48	0	0
T5	441	2	0	0
T6	394	11	0	0
T7	431	6	0	0
T8	344	7	0	0
T9	334	6	0	0
T10	195	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	1083	0	0
T1	8477	26	0	0
T2	372	0	0	0
T3	482	0	0	0
T4	3974	0	0	0
T5	441	0	0	0
T6	394	10	0	0
T7	431	0	0	0
T8	344	1	0	0
T9	334	0	0	0
T10	195	0	0	0
T36	0	4	0	0
T49	0	5	0	0
T52	0	8	0	0
T53	0	5	0	0
T54	0	7	0	0
T71	0	10	0	0
T72	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	22689	0	0
T1	8477	164	0	0
T2	372	6	0	0
T3	482	6	0	0
T4	3974	48	0	0
T5	441	2	0	0
T6	394	11	0	0
T7	431	6	0	0
T8	344	7	0	0
T9	334	6	0	0
T10	195	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	1083	0	0
T1	8477	26	0	0
T2	372	0	0	0
T3	482	0	0	0
T4	3974	0	0	0
T5	441	0	0	0
T6	394	10	0	0
T7	431	0	0	0
T8	344	1	0	0
T9	334	0	0	0
T10	195	0	0	0
T36	0	4	0	0
T49	0	5	0	0
T52	0	8	0	0
T53	0	5	0	0
T54	0	7	0	0
T71	0	10	0	0
T72	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	15175	0	0
T1	66701	113	0	0
T2	2990	5	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	9	0	0
T7	3460	4	0	0
T8	2761	4	0	0
T9	2679	4	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1147	0	0
T1	66701	27	0	0
T2	2990	1	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	9	0	0
T7	3460	0	0	0
T8	2761	0	0	0
T9	2679	0	0	0
T10	1565	0	0	0
T36	0	6	0	0
T49	0	3	0	0
T52	0	8	0	0
T53	0	6	0	0
T54	0	7	0	0
T71	0	12	0	0
T72	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	15175	0	0
T1	66701	113	0	0
T2	2990	5	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	9	0	0
T7	3460	4	0	0
T8	2761	4	0	0
T9	2679	4	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1147	0	0
T1	66701	27	0	0
T2	2990	1	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	9	0	0
T7	3460	0	0	0
T8	2761	0	0	0
T9	2679	0	0	0
T10	1565	0	0	0
T36	0	6	0	0
T49	0	3	0	0
T52	0	8	0	0
T53	0	6	0	0
T54	0	7	0	0
T71	0	12	0	0
T72	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	15236	0	0
T1	66701	114	0	0
T2	2990	4	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	4	0	0
T8	2761	5	0	0
T9	2679	4	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1204	0	0
T1	66701	27	0	0
T2	2990	0	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	0	0	0
T8	2761	1	0	0
T9	2679	0	0	0
T10	1565	0	0	0
T36	0	7	0	0
T49	0	6	0	0
T52	0	9	0	0
T53	0	7	0	0
T63	0	1	0	0
T71	0	10	0	0
T72	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	15236	0	0
T1	66701	114	0	0
T2	2990	4	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	4	0	0
T8	2761	5	0	0
T9	2679	4	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1204	0	0
T1	66701	27	0	0
T2	2990	0	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	0	0	0
T8	2761	1	0	0
T9	2679	0	0	0
T10	1565	0	0	0
T36	0	7	0	0
T49	0	6	0	0
T52	0	9	0	0
T53	0	7	0	0
T63	0	1	0	0
T71	0	10	0	0
T72	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	15267	0	0
T1	66701	114	0	0
T2	2990	5	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	4	0	0
T8	2761	4	0	0
T9	2679	4	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1234	0	0
T1	66701	27	0	0
T2	2990	1	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	0	0	0
T8	2761	0	0	0
T9	2679	0	0	0
T10	1565	0	0	0
T36	0	7	0	0
T49	0	5	0	0
T52	0	11	0	0
T53	0	7	0	0
T63	0	1	0	0
T71	0	11	0	0
T72	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	15267	0	0
T1	66701	114	0	0
T2	2990	5	0	0
T3	3871	4	0	0
T4	31291	31	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	4	0	0
T8	2761	4	0	0
T9	2679	4	0	0
T10	1565	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	1234	0	0
T1	66701	27	0	0
T2	2990	1	0	0
T3	3871	0	0	0
T4	31291	0	0	0
T5	3540	0	0	0
T6	3156	12	0	0
T7	3460	0	0	0
T8	2761	0	0	0
T9	2679	0	0	0
T10	1565	0	0	0
T36	0	7	0	0
T49	0	5	0	0
T52	0	11	0	0
T53	0	7	0	0
T63	0	1	0	0
T71	0	11	0	0
T72	0	9	0	0