Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12577156	9184	0	0
alert_regwen_rd_A	12577156	5529	0	0
cpu_regwen_rd_A	12577156	5405	0	0
sw_rst_ctrl_n_0_rd_A	12577156	8310	0	0
sw_rst_ctrl_n_1_rd_A	12577156	8644	0	0
sw_rst_ctrl_n_2_rd_A	12577156	8640	0	0
sw_rst_ctrl_n_3_rd_A	12577156	8718	0	0
sw_rst_ctrl_n_4_rd_A	12577156	8528	0	0
sw_rst_ctrl_n_5_rd_A	12577156	8773	0	0
sw_rst_ctrl_n_6_rd_A	12577156	8719	0	0
sw_rst_ctrl_n_7_rd_A	12577156	8611	0	0
sw_rst_regwen_0_rd_A	12577156	5446	0	0
sw_rst_regwen_1_rd_A	12577156	5648	0	0
sw_rst_regwen_2_rd_A	12577156	5531	0	0
sw_rst_regwen_3_rd_A	12577156	5818	0	0
sw_rst_regwen_4_rd_A	12577156	5877	0	0
sw_rst_regwen_5_rd_A	12577156	5803	0	0
sw_rst_regwen_6_rd_A	12577156	5750	0	0
sw_rst_regwen_7_rd_A	12577156	5668	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	9184	0	0
T73	2710	63	0	0
T74	3517	19	0	0
T79	6213	304	0	0
T80	10389	1	0	0
T81	10317	705	0	0
T82	20907	4	0	0
T87	2673	2	0	0
T88	4920	459	0	0
T89	3148	16	0	0
T90	10849	618	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5529	0	0
T18	5145	0	0	0
T42	26014	0	0	0
T49	54163	67	0	0
T50	5286	0	0	0
T51	4851	0	0	0
T52	9800	0	0	0
T53	2598	0	0	0
T54	3406	0	0	0
T93	73877	0	0	0
T95	0	56	0	0
T98	0	82	0	0
T100	1571	0	0	0
T102	0	62	0	0
T103	0	404	0	0
T105	0	77	0	0
T126	0	63	0	0
T127	0	70	0	0
T128	0	61	0	0
T129	0	89	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5405	0	0
T18	5145	0	0	0
T42	26014	0	0	0
T49	54163	77	0	0
T50	5286	0	0	0
T51	4851	0	0	0
T52	9800	0	0	0
T53	2598	0	0	0
T54	3406	0	0	0
T93	73877	0	0	0
T95	0	47	0	0
T98	0	85	0	0
T100	1571	0	0	0
T102	0	44	0	0
T103	0	351	0	0
T105	0	65	0	0
T126	0	62	0	0
T127	0	59	0	0
T128	0	43	0	0
T129	0	78	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8310	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	89	0	0
T49	0	182	0	0
T51	0	28	0	0
T52	0	150	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	10	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	57	0	0
T98	0	81	0	0
T130	0	3	0	0
T131	0	48	0	0
T132	0	43	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8644	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	99	0	0
T49	0	162	0	0
T51	0	22	0	0
T52	0	129	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	7	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	53	0	0
T98	0	92	0	0
T130	0	12	0	0
T131	0	49	0	0
T132	0	58	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8640	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	132	0	0
T49	0	151	0	0
T51	0	33	0	0
T52	0	141	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	15	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	46	0	0
T98	0	89	0	0
T130	0	3	0	0
T131	0	38	0	0
T132	0	54	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8718	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	146	0	0
T49	0	133	0	0
T51	0	26	0	0
T52	0	123	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	21	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	55	0	0
T98	0	80	0	0
T130	0	13	0	0
T131	0	46	0	0
T132	0	61	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8528	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	100	0	0
T49	0	129	0	0
T51	0	37	0	0
T52	0	162	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	14	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	56	0	0
T98	0	94	0	0
T130	0	2	0	0
T131	0	46	0	0
T132	0	49	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8773	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	135	0	0
T49	0	127	0	0
T51	0	43	0	0
T52	0	136	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	23	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	50	0	0
T98	0	107	0	0
T130	0	1	0	0
T131	0	70	0	0
T132	0	69	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8719	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	133	0	0
T49	0	145	0	0
T51	0	41	0	0
T52	0	172	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	18	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	53	0	0
T98	0	103	0	0
T130	0	12	0	0
T131	0	27	0	0
T132	0	54	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	8611	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	108	0	0
T49	0	156	0	0
T51	0	46	0	0
T52	0	141	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	14	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	57	0	0
T98	0	104	0	0
T130	0	5	0	0
T131	0	37	0	0
T132	0	32	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5446	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	39	0	0
T49	0	97	0	0
T52	0	20	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	5	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	46	0	0
T98	0	85	0	0
T130	0	6	0	0
T133	0	30	0	0
T134	0	8	0	0
T135	0	38	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5648	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	24	0	0
T49	0	75	0	0
T52	0	33	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	1	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	44	0	0
T98	0	93	0	0
T130	0	9	0	0
T133	0	30	0	0
T134	0	7	0	0
T135	0	35	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5531	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	31	0	0
T49	0	61	0	0
T52	0	35	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	14	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	61	0	0
T98	0	109	0	0
T102	0	47	0	0
T133	0	40	0	0
T134	0	13	0	0
T135	0	35	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5818	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	32	0	0
T49	0	89	0	0
T52	0	49	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	7	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	38	0	0
T98	0	106	0	0
T130	0	12	0	0
T133	0	24	0	0
T134	0	13	0	0
T135	0	38	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5877	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	34	0	0
T49	0	66	0	0
T52	0	30	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	8	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	69	0	0
T98	0	102	0	0
T102	0	30	0	0
T133	0	17	0	0
T134	0	5	0	0
T135	0	38	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5803	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	30	0	0
T49	0	83	0	0
T52	0	37	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	11	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	50	0	0
T98	0	80	0	0
T130	0	8	0	0
T133	0	35	0	0
T134	0	4	0	0
T135	0	22	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5750	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	26	0	0
T49	0	37	0	0
T52	0	38	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	3	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	52	0	0
T98	0	89	0	0
T130	0	3	0	0
T133	0	37	0	0
T134	0	3	0	0
T135	0	26	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12577156	5668	0	0
T15	2311	0	0	0
T16	5996	0	0	0
T24	26231	0	0	0
T34	25400	0	0	0
T36	0	47	0	0
T49	0	58	0	0
T52	0	33	0	0
T57	3891	0	0	0
T58	5475	0	0	0
T63	5841	9	0	0
T64	1305	0	0	0
T65	5670	0	0	0
T66	3500	0	0	0
T95	0	30	0	0
T98	0	73	0	0
T130	0	4	0	0
T133	0	35	0	0
T134	0	7	0	0
T135	0	25	0	0