Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T9,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55410138	8881	0	0
CascadeEffAonToRstPorAboveRise_A	55410138	8881	0	0
CascadeEffAonToRstPorIoAboveFall_A	53192184	8881	0	0
CascadeEffAonToRstPorIoAboveRise_A	53192184	8881	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26597063	8881	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26597063	8881	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13298126	8881	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13298126	8881	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26597323	8881	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26597323	8881	0	0
CascadeLcToLcAboveFall_A	55410138	22944	0	0
CascadeLcToLcAboveRise_A	55410138	22944	0	0
CascadeLcToLcAonAboveFall_A	1680483	22944	0	0
CascadeLcToLcAonAboveRise_A	1680483	22944	0	0
CascadeLcToLcShadowedAboveFall_A	55410138	22944	0	0
CascadeLcToLcShadowedAboveRise_A	55410138	22944	0	0
CascadePorToAonAboveFall_A	1680483	6907	0	0
CascadeSysToSysAboveFall_A	55410138	22944	0	0
CascadeSysToSysAboveRise_A	55410138	22944	0	0
ScanRstToAonRise_A	1680483	222	0	0
StablePorToAonRise_A	1680483	8881	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11741424	22944	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11741424	22944	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11741424	22944	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11741424	22944	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13298126	22944	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13298126	22944	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11741424	22944	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11741424	22944	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11741424	22944	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11741424	22944	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	8881	0	0
T1	277918	57	0	0
T2	12470	2	0	0
T3	16139	2	0	0
T4	130384	17	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	2	0	0
T8	11505	2	0	0
T9	11167	2	0	0
T10	6527	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	8881	0	0
T1	277918	57	0	0
T2	12470	2	0	0
T3	16139	2	0	0
T4	130384	17	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	2	0	0
T8	11505	2	0	0
T9	11167	2	0	0
T10	6527	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53192184	8881	0	0
T1	266792	57	0	0
T2	11963	2	0	0
T3	15491	2	0	0
T4	125142	17	0	0
T5	14161	2	0	0
T6	12632	1	0	0
T7	13853	2	0	0
T8	11048	2	0	0
T9	10719	2	0	0
T10	6265	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53192184	8881	0	0
T1	266792	57	0	0
T2	11963	2	0	0
T3	15491	2	0	0
T4	125142	17	0	0
T5	14161	2	0	0
T6	12632	1	0	0
T7	13853	2	0	0
T8	11048	2	0	0
T9	10719	2	0	0
T10	6265	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597063	8881	0	0
T1	133401	57	0	0
T2	5982	2	0	0
T3	7745	2	0	0
T4	62590	17	0	0
T5	7080	2	0	0
T6	6315	1	0	0
T7	6926	2	0	0
T8	5524	2	0	0
T9	5357	2	0	0
T10	3132	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597063	8881	0	0
T1	133401	57	0	0
T2	5982	2	0	0
T3	7745	2	0	0
T4	62590	17	0	0
T5	7080	2	0	0
T6	6315	1	0	0
T7	6926	2	0	0
T8	5524	2	0	0
T9	5357	2	0	0
T10	3132	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	8881	0	0
T1	66701	57	0	0
T2	2990	2	0	0
T3	3871	2	0	0
T4	31291	17	0	0
T5	3540	2	0	0
T6	3156	1	0	0
T7	3460	2	0	0
T8	2761	2	0	0
T9	2679	2	0	0
T10	1565	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	8881	0	0
T1	66701	57	0	0
T2	2990	2	0	0
T3	3871	2	0	0
T4	31291	17	0	0
T5	3540	2	0	0
T6	3156	1	0	0
T7	3460	2	0	0
T8	2761	2	0	0
T9	2679	2	0	0
T10	1565	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597323	8881	0	0
T1	133403	57	0	0
T2	5983	2	0	0
T3	7744	2	0	0
T4	62584	17	0	0
T5	7080	2	0	0
T6	6315	1	0	0
T7	6925	2	0	0
T8	5524	2	0	0
T9	5359	2	0	0
T10	3132	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26597323	8881	0	0
T1	133403	57	0	0
T2	5983	2	0	0
T3	7744	2	0	0
T4	62584	17	0	0
T5	7080	2	0	0
T6	6315	1	0	0
T7	6925	2	0	0
T8	5524	2	0	0
T9	5359	2	0	0
T10	3132	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	22944	0	0
T1	277918	145	0	0
T2	12470	6	0	0
T3	16139	6	0	0
T4	130384	48	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	6	0	0
T8	11505	6	0	0
T9	11167	6	0	0
T10	6527	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	22944	0	0
T1	277918	145	0	0
T2	12470	6	0	0
T3	16139	6	0	0
T4	130384	48	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	6	0	0
T8	11505	6	0	0
T9	11167	6	0	0
T10	6527	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	22944	0	0
T1	8477	145	0	0
T2	372	6	0	0
T3	482	6	0	0
T4	3974	48	0	0
T5	441	2	0	0
T6	394	1	0	0
T7	431	6	0	0
T8	344	6	0	0
T9	334	6	0	0
T10	195	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	22944	0	0
T1	8477	145	0	0
T2	372	6	0	0
T3	482	6	0	0
T4	3974	48	0	0
T5	441	2	0	0
T6	394	1	0	0
T7	431	6	0	0
T8	344	6	0	0
T9	334	6	0	0
T10	195	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	22944	0	0
T1	277918	145	0	0
T2	12470	6	0	0
T3	16139	6	0	0
T4	130384	48	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	6	0	0
T8	11505	6	0	0
T9	11167	6	0	0
T10	6527	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	22944	0	0
T1	277918	145	0	0
T2	12470	6	0	0
T3	16139	6	0	0
T4	130384	48	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	6	0	0
T8	11505	6	0	0
T9	11167	6	0	0
T10	6527	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	6907	0	0
T1	8477	30	0	0
T2	372	1	0	0
T3	482	1	0	0
T4	3974	10	0	0
T5	441	10	0	0
T6	394	1	0	0
T7	431	1	0	0
T8	344	1	0	0
T9	334	1	0	0
T10	195	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	22944	0	0
T1	277918	145	0	0
T2	12470	6	0	0
T3	16139	6	0	0
T4	130384	48	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	6	0	0
T8	11505	6	0	0
T9	11167	6	0	0
T10	6527	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55410138	22944	0	0
T1	277918	145	0	0
T2	12470	6	0	0
T3	16139	6	0	0
T4	130384	48	0	0
T5	14751	2	0	0
T6	13159	1	0	0
T7	14432	6	0	0
T8	11505	6	0	0
T9	11167	6	0	0
T10	6527	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	222	0	0
T2	372	1	0	0
T3	482	0	0	0
T4	3974	1	0	0
T5	441	0	0	0
T6	394	0	0	0
T7	431	0	0	0
T8	344	0	0	0
T9	334	0	0	0
T10	195	0	0	0
T11	460	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T63	0	1	0	0
T93	0	4	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	4	0	0
T97	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680483	8881	0	0
T1	8477	57	0	0
T2	372	2	0	0
T3	482	2	0	0
T4	3974	17	0	0
T5	441	2	0	0
T6	394	1	0	0
T7	431	2	0	0
T8	344	2	0	0
T9	334	2	0	0
T10	195	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	22944	0	0
T1	66701	145	0	0
T2	2990	6	0	0
T3	3871	6	0	0
T4	31291	48	0	0
T5	3540	2	0	0
T6	3156	1	0	0
T7	3460	6	0	0
T8	2761	6	0	0
T9	2679	6	0	0
T10	1565	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13298126	22944	0	0
T1	66701	145	0	0
T2	2990	6	0	0
T3	3871	6	0	0
T4	31291	48	0	0
T5	3540	2	0	0
T6	3156	1	0	0
T7	3460	6	0	0
T8	2761	6	0	0
T9	2679	6	0	0
T10	1565	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11741424	22944	0	0
T1	55668	145	0	0
T2	2795	6	0	0
T3	3484	6	0	0
T4	26758	48	0	0
T5	3425	2	0	0
T6	3067	1	0	0
T7	3173	6	0	0
T8	2470	6	0	0
T9	2393	6	0	0
T10	1475	1	0	0