Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	609661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

365313

1

T1

320

T2

5779

T3

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	520006	1			T1	419		T2	8578		T3	186
values[0x0]	227044	1			T1	199		T2	3434		T3	90
values[0x1]	227924	1			T1	174		T2	3516		T3	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	511431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

463543

1

T1

382

T2

7345

T3

183

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3820	1			T1	1		T2	88		T4	16
valid_sources[0x01]	4439	1			T1	1		T2	83		T4	11
valid_sources[0x02]	3423	1			T1	4		T2	74		T3	1
valid_sources[0x03]	6975	1			T1	2		T2	88		T4	8
valid_sources[0x04]	3802	1			T2	16		T3	21		T4	6
valid_sources[0x05]	3812	1			T2	41		T3	6		T4	11
valid_sources[0x06]	4422	1			T1	11		T2	52		T4	9
valid_sources[0x07]	3578	1			T1	8		T2	57		T4	8
valid_sources[0x08]	3204	1			T1	1		T2	57		T3	65
valid_sources[0x09]	2985	1			T1	11		T2	34		T4	10
valid_sources[0x0a]	3567	1			T1	3		T2	51		T4	2
valid_sources[0x0b]	2944	1			T1	6		T2	55		T4	6
valid_sources[0x0c]	3039	1			T2	108		T4	8		T10	25
valid_sources[0x0d]	4602	1			T1	6		T2	65		T3	9
valid_sources[0x0e]	3202	1			T2	46		T4	4		T9	1
valid_sources[0x0f]	3198	1			T2	31		T3	30		T8	1
valid_sources[0x10]	3675	1			T2	44		T4	12		T8	1
valid_sources[0x11]	3528	1			T2	23		T4	3		T10	32
valid_sources[0x12]	3224	1			T2	33		T4	7		T9	5
valid_sources[0x13]	3381	1			T1	8		T2	62		T4	15
valid_sources[0x14]	4650	1			T2	35		T4	12		T10	38
valid_sources[0x15]	3370	1			T2	39		T3	12		T4	10
valid_sources[0x16]	3195	1			T1	2		T2	75		T4	4
valid_sources[0x17]	4788	1			T2	34		T4	3		T9	1
valid_sources[0x18]	3705	1			T1	3		T2	86		T4	2
valid_sources[0x19]	4270	1			T2	42		T4	14		T10	31
valid_sources[0x1a]	3207	1			T1	5		T2	68		T4	18
valid_sources[0x1b]	3528	1			T1	1		T2	90		T4	7
valid_sources[0x1c]	4152	1			T2	36		T4	6		T9	2
valid_sources[0x1d]	3368	1			T1	1		T2	26		T4	3
valid_sources[0x1e]	6158	1			T2	67		T3	10		T4	14
valid_sources[0x1f]	3277	1			T1	3		T2	64		T4	3
valid_sources[0x20]	2874	1			T1	1		T2	64		T3	32
valid_sources[0x21]	3149	1			T2	66		T4	5		T10	38
valid_sources[0x22]	3451	1			T2	33		T4	11		T10	36
valid_sources[0x23]	3011	1			T2	128		T4	12		T9	3
valid_sources[0x24]	4022	1			T1	15		T2	33		T4	12
valid_sources[0x25]	3459	1			T1	3		T2	73		T3	2
valid_sources[0x26]	4444	1			T2	30		T4	4		T9	2
valid_sources[0x27]	3201	1			T2	48		T4	13		T10	27
valid_sources[0x28]	3659	1			T2	51		T4	12		T10	33
valid_sources[0x29]	4409	1			T1	1		T2	73		T4	8
valid_sources[0x2a]	4756	1			T2	55		T4	3		T9	3
valid_sources[0x2b]	5132	1			T1	1		T2	56		T4	10
valid_sources[0x2c]	3791	1			T2	44		T4	5		T9	1
valid_sources[0x2d]	3290	1			T2	53		T4	10		T10	22
valid_sources[0x2e]	3216	1			T1	4		T2	51		T4	9
valid_sources[0x2f]	3518	1			T2	31		T4	9		T10	32
valid_sources[0x30]	3406	1			T1	22		T2	44		T4	6
valid_sources[0x31]	3009	1			T1	3		T2	50		T4	8
valid_sources[0x32]	3225	1			T2	46		T4	13		T9	2
valid_sources[0x33]	4094	1			T2	62		T4	16		T6	1
valid_sources[0x34]	3258	1			T2	82		T4	4		T10	24
valid_sources[0x35]	4503	1			T1	2		T2	53		T4	3
valid_sources[0x36]	3077	1			T2	32		T4	12		T10	30
valid_sources[0x37]	3121	1			T2	162		T4	19		T8	1
valid_sources[0x38]	3161	1			T2	75		T4	6		T9	1
valid_sources[0x39]	3042	1			T2	38		T4	3		T8	1
valid_sources[0x3a]	3375	1			T1	5		T2	86		T4	14
valid_sources[0x3b]	6688	1			T1	9		T2	34		T4	11
valid_sources[0x3c]	3994	1			T1	2		T2	59		T4	4
valid_sources[0x3d]	3586	1			T2	67		T4	3		T10	29
valid_sources[0x3e]	4213	1			T2	103		T4	8		T10	26
valid_sources[0x3f]	3560	1			T1	2		T2	31		T3	16
valid_sources[0x40]	3666	1			T1	2		T2	54		T4	32
valid_sources[0x41]	3788	1			T1	1		T2	52		T4	5
valid_sources[0x42]	7982	1			T1	3		T2	81		T4	9
valid_sources[0x43]	3228	1			T2	80		T3	7		T4	18
valid_sources[0x44]	3349	1			T2	46		T4	5		T10	30
valid_sources[0x45]	3515	1			T2	91		T4	9		T8	1
valid_sources[0x46]	3316	1			T2	74		T4	3		T8	2
valid_sources[0x47]	3704	1			T2	39		T4	11		T9	2
valid_sources[0x48]	4051	1			T1	6		T2	64		T4	5
valid_sources[0x49]	3592	1			T2	91		T4	2		T8	1
valid_sources[0x4a]	3447	1			T1	2		T2	44		T4	8
valid_sources[0x4b]	3395	1			T2	45		T4	16		T8	1
valid_sources[0x4c]	3406	1			T1	18		T2	50		T3	1
valid_sources[0x4d]	3792	1			T2	116		T4	15		T10	41
valid_sources[0x4e]	3368	1			T1	8		T2	52		T4	7
valid_sources[0x4f]	3590	1			T1	24		T2	61		T4	3
valid_sources[0x50]	3126	1			T1	2		T2	107		T3	21
valid_sources[0x51]	3487	1			T1	6		T2	49		T4	19
valid_sources[0x52]	3497	1			T1	7		T2	30		T3	4
valid_sources[0x53]	3623	1			T1	6		T2	124		T4	4
valid_sources[0x54]	3511	1			T2	83		T4	2		T10	32
valid_sources[0x55]	3812	1			T1	4		T2	33		T4	17
valid_sources[0x56]	3219	1			T1	1		T2	77		T4	2
valid_sources[0x57]	3646	1			T2	30		T4	7		T10	25
valid_sources[0x58]	5627	1			T2	96		T4	10		T6	1
valid_sources[0x59]	3641	1			T2	57		T4	9		T9	2
valid_sources[0x5a]	3000	1			T2	65		T4	5		T9	4
valid_sources[0x5b]	5006	1			T2	83		T4	10		T10	26
valid_sources[0x5c]	3219	1			T1	8		T2	80		T4	19
valid_sources[0x5d]	3747	1			T1	2		T2	101		T4	1
valid_sources[0x5e]	3974	1			T2	23		T4	2		T9	3
valid_sources[0x5f]	3975	1			T1	19		T2	59		T4	3
valid_sources[0x60]	3436	1			T1	5		T2	73		T4	9
valid_sources[0x61]	4406	1			T1	3		T2	91		T4	6
valid_sources[0x62]	4092	1			T2	35		T4	8		T10	28
valid_sources[0x63]	3116	1			T1	6		T2	39		T4	2
valid_sources[0x64]	3524	1			T2	39		T4	5		T6	1
valid_sources[0x65]	3558	1			T2	56		T4	12		T10	31
valid_sources[0x66]	4037	1			T1	6		T2	23		T4	7
valid_sources[0x67]	3402	1			T1	2		T2	76		T4	4
valid_sources[0x68]	3615	1			T2	74		T4	8		T9	2
valid_sources[0x69]	3362	1			T1	1		T2	92		T4	2
valid_sources[0x6a]	3148	1			T1	4		T2	57		T4	12
valid_sources[0x6b]	3475	1			T1	9		T2	62		T4	4
valid_sources[0x6c]	3910	1			T2	105		T4	6		T8	1
valid_sources[0x6d]	4284	1			T1	1		T2	45		T4	7
valid_sources[0x6e]	4240	1			T2	54		T4	14		T9	2
valid_sources[0x6f]	4782	1			T1	2		T2	51		T4	15
valid_sources[0x70]	4080	1			T2	90		T4	11		T10	32
valid_sources[0x71]	4363	1			T1	8		T2	59		T4	11
valid_sources[0x72]	4294	1			T2	65		T4	1		T10	41
valid_sources[0x73]	3684	1			T1	4		T2	67		T4	8
valid_sources[0x74]	3738	1			T1	7		T2	60		T4	5
valid_sources[0x75]	3317	1			T1	6		T2	39		T4	14
valid_sources[0x76]	3965	1			T2	127		T4	11		T9	1
valid_sources[0x77]	3793	1			T2	62		T4	7		T9	4
valid_sources[0x78]	4068	1			T1	10		T2	47		T4	6
valid_sources[0x79]	3706	1			T2	93		T4	5		T9	6
valid_sources[0x7a]	3730	1			T1	1		T2	80		T4	8
valid_sources[0x7b]	4327	1			T1	5		T2	36		T3	14
valid_sources[0x7c]	3851	1			T1	1		T2	45		T4	12
valid_sources[0x7d]	3327	1			T1	4		T2	68		T3	13
valid_sources[0x7e]	3110	1			T2	28		T4	9		T9	3
valid_sources[0x7f]	3516	1			T2	17		T4	8		T6	1
valid_sources[0x80]	3581	1			T2	20		T4	3		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

244130

1

T1

221

T2

4026

T3

85

values[0x0]

all_enables

biggest_size

79010

1

T1

70

T2

1137

T3

30

values[0x1]

all_enables

biggest_size

42173

1

T1

29

T2

616

T3

14