Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11804359	13019	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11804359	119967	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11804359	6964257	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11804359	191262	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11804359	13019	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11804359	119967	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11804359	6964257	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11804359	191262	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	13019	0	0
T2	98766	192	0	0
T3	4333	4	0	0
T4	31719	31	0	0
T5	4697	0	0	0
T6	1263	1	0	0
T7	4428	0	0	0
T8	1463	1	0	0
T9	5694	4	0	0
T10	47624	109	0	0
T11	3961	15	0	0
T20	0	4	0	0
T21	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	119967	0	0
T2	98766	1735	0	0
T3	4333	37	0	0
T4	31719	286	0	0
T5	4697	0	0	0
T6	1263	9	0	0
T7	4428	0	0	0
T8	1463	9	0	0
T9	5694	38	0	0
T10	47624	1010	0	0
T11	3961	135	0	0
T20	0	37	0	0
T21	0	37	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	6964257	0	0
T1	2905	2259	0	0
T2	98766	48327	0	0
T3	4333	3379	0	0
T4	31719	25067	0	0
T5	4697	839	0	0
T6	1263	650	0	0
T7	4428	779	0	0
T8	1463	882	0	0
T9	5694	4708	0	0
T10	47624	23807	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	191262	0	0
T2	98766	2812	0	0
T3	4333	58	0	0
T4	31719	429	0	0
T5	4697	0	0	0
T6	1263	11	0	0
T7	4428	0	0	0
T8	1463	16	0	0
T9	5694	55	0	0
T10	47624	1614	0	0
T11	3961	213	0	0
T20	0	59	0	0
T21	0	49	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	13019	0	0
T2	98766	192	0	0
T3	4333	4	0	0
T4	31719	31	0	0
T5	4697	0	0	0
T6	1263	1	0	0
T7	4428	0	0	0
T8	1463	1	0	0
T9	5694	4	0	0
T10	47624	109	0	0
T11	3961	15	0	0
T20	0	4	0	0
T21	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	119967	0	0
T2	98766	1735	0	0
T3	4333	37	0	0
T4	31719	286	0	0
T5	4697	0	0	0
T6	1263	9	0	0
T7	4428	0	0	0
T8	1463	9	0	0
T9	5694	38	0	0
T10	47624	1010	0	0
T11	3961	135	0	0
T20	0	37	0	0
T21	0	37	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	6964257	0	0
T1	2905	2259	0	0
T2	98766	48327	0	0
T3	4333	3379	0	0
T4	31719	25067	0	0
T5	4697	839	0	0
T6	1263	650	0	0
T7	4428	779	0	0
T8	1463	882	0	0
T9	5694	4708	0	0
T10	47624	23807	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	191262	0	0
T2	98766	2812	0	0
T3	4333	58	0	0
T4	31719	429	0	0
T5	4697	0	0	0
T6	1263	11	0	0
T7	4428	0	0	0
T8	1463	16	0	0
T9	5694	55	0	0
T10	47624	1614	0	0
T11	3961	213	0	0
T20	0	59	0	0
T21	0	49	0	0