Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T4,T10
1	0	Covered	T2,T4,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55205783	8837	0	0
CascadeEffAonToRstPorAboveRise_A	55205783	8837	0	0
CascadeEffAonToRstPorIoAboveFall_A	52995196	8837	0	0
CascadeEffAonToRstPorIoAboveRise_A	52995196	8837	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26498943	8837	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26498943	8837	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13248960	8837	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13248960	8837	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26498824	8837	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26498824	8837	0	0
CascadeLcToLcAboveFall_A	55205783	21856	0	0
CascadeLcToLcAboveRise_A	55205783	21856	0	0
CascadeLcToLcAonAboveFall_A	1672342	21856	0	0
CascadeLcToLcAonAboveRise_A	1672342	21856	0	0
CascadeLcToLcShadowedAboveFall_A	55205783	21856	0	0
CascadeLcToLcShadowedAboveRise_A	55205783	21856	0	0
CascadePorToAonAboveFall_A	1672342	7133	0	0
CascadeSysToSysAboveFall_A	55205783	21856	0	0
CascadeSysToSysAboveRise_A	55205783	21856	0	0
ScanRstToAonRise_A	1672342	229	0	0
StablePorToAonRise_A	1672342	8837	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11804359	21856	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11804359	21856	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11804359	21856	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11804359	21856	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13248960	21856	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13248960	21856	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11804359	21856	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11804359	21856	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11804359	21856	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11804359	21856	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	8837	0	0
T1	12187	1	0	0
T2	509826	106	0	0
T3	18867	2	0	0
T4	149837	14	0	0
T5	20053	2	0	0
T6	5761	1	0	0
T7	19031	2	0	0
T8	6883	1	0	0
T9	24920	2	0	0
T10	251281	52	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	8837	0	0
T1	12187	1	0	0
T2	509826	106	0	0
T3	18867	2	0	0
T4	149837	14	0	0
T5	20053	2	0	0
T6	5761	1	0	0
T7	19031	2	0	0
T8	6883	1	0	0
T9	24920	2	0	0
T10	251281	52	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52995196	8837	0	0
T1	11699	1	0	0
T2	489442	106	0	0
T3	18117	2	0	0
T4	143820	14	0	0
T5	19250	2	0	0
T6	5530	1	0	0
T7	18269	2	0	0
T8	6608	1	0	0
T9	23926	2	0	0
T10	241233	52	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52995196	8837	0	0
T1	11699	1	0	0
T2	489442	106	0	0
T3	18117	2	0	0
T4	143820	14	0	0
T5	19250	2	0	0
T6	5530	1	0	0
T7	18269	2	0	0
T8	6608	1	0	0
T9	23926	2	0	0
T10	241233	52	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498943	8837	0	0
T1	5850	1	0	0
T2	244741	106	0	0
T3	9060	2	0	0
T4	71927	14	0	0
T5	9624	2	0	0
T6	2764	1	0	0
T7	9135	2	0	0
T8	3303	1	0	0
T9	11962	2	0	0
T10	120616	52	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498943	8837	0	0
T1	5850	1	0	0
T2	244741	106	0	0
T3	9060	2	0	0
T4	71927	14	0	0
T5	9624	2	0	0
T6	2764	1	0	0
T7	9135	2	0	0
T8	3303	1	0	0
T9	11962	2	0	0
T10	120616	52	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	8837	0	0
T1	2924	1	0	0
T2	122376	106	0	0
T3	4527	2	0	0
T4	35957	14	0	0
T5	4811	2	0	0
T6	1383	1	0	0
T7	4566	2	0	0
T8	1650	1	0	0
T9	5980	2	0	0
T10	60315	52	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	8837	0	0
T1	2924	1	0	0
T2	122376	106	0	0
T3	4527	2	0	0
T4	35957	14	0	0
T5	4811	2	0	0
T6	1383	1	0	0
T7	4566	2	0	0
T8	1650	1	0	0
T9	5980	2	0	0
T10	60315	52	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498824	8837	0	0
T1	5849	1	0	0
T2	244720	106	0	0
T3	9056	2	0	0
T4	71934	14	0	0
T5	9624	2	0	0
T6	2764	1	0	0
T7	9134	2	0	0
T8	3304	1	0	0
T9	11961	2	0	0
T10	120606	52	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498824	8837	0	0
T1	5849	1	0	0
T2	244720	106	0	0
T3	9056	2	0	0
T4	71934	14	0	0
T5	9624	2	0	0
T6	2764	1	0	0
T7	9134	2	0	0
T8	3304	1	0	0
T9	11961	2	0	0
T10	120606	52	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	21856	0	0
T1	12187	1	0	0
T2	509826	298	0	0
T3	18867	6	0	0
T4	149837	45	0	0
T5	20053	2	0	0
T6	5761	2	0	0
T7	19031	2	0	0
T8	6883	2	0	0
T9	24920	6	0	0
T10	251281	161	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	21856	0	0
T1	12187	1	0	0
T2	509826	298	0	0
T3	18867	6	0	0
T4	149837	45	0	0
T5	20053	2	0	0
T6	5761	2	0	0
T7	19031	2	0	0
T8	6883	2	0	0
T9	24920	6	0	0
T10	251281	161	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	21856	0	0
T1	364	1	0	0
T2	15709	298	0	0
T3	566	6	0	0
T4	4557	45	0	0
T5	599	2	0	0
T6	171	2	0	0
T7	569	2	0	0
T8	206	2	0	0
T9	746	6	0	0
T10	7820	161	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	21856	0	0
T1	364	1	0	0
T2	15709	298	0	0
T3	566	6	0	0
T4	4557	45	0	0
T5	599	2	0	0
T6	171	2	0	0
T7	569	2	0	0
T8	206	2	0	0
T9	746	6	0	0
T10	7820	161	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	21856	0	0
T1	12187	1	0	0
T2	509826	298	0	0
T3	18867	6	0	0
T4	149837	45	0	0
T5	20053	2	0	0
T6	5761	2	0	0
T7	19031	2	0	0
T8	6883	2	0	0
T9	24920	6	0	0
T10	251281	161	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	21856	0	0
T1	12187	1	0	0
T2	509826	298	0	0
T3	18867	6	0	0
T4	149837	45	0	0
T5	20053	2	0	0
T6	5761	2	0	0
T7	19031	2	0	0
T8	6883	2	0	0
T9	24920	6	0	0
T10	251281	161	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	7133	0	0
T1	364	1	0	0
T2	15709	60	0	0
T3	566	1	0	0
T4	4557	9	0	0
T5	599	18	0	0
T6	171	1	0	0
T7	569	17	0	0
T8	206	1	0	0
T9	746	1	0	0
T10	7820	26	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	21856	0	0
T1	12187	1	0	0
T2	509826	298	0	0
T3	18867	6	0	0
T4	149837	45	0	0
T5	20053	2	0	0
T6	5761	2	0	0
T7	19031	2	0	0
T8	6883	2	0	0
T9	24920	6	0	0
T10	251281	161	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55205783	21856	0	0
T1	12187	1	0	0
T2	509826	298	0	0
T3	18867	6	0	0
T4	149837	45	0	0
T5	20053	2	0	0
T6	5761	2	0	0
T7	19031	2	0	0
T8	6883	2	0	0
T9	24920	6	0	0
T10	251281	161	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	229	0	0
T2	15709	4	0	0
T3	566	0	0	0
T4	4557	0	0	0
T5	599	0	0	0
T6	171	0	0	0
T7	569	0	0	0
T8	206	0	0	0
T9	746	0	0	0
T10	7820	1	0	0
T11	614	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T81	0	5	0	0
T85	0	1	0	0
T93	0	5	0	0
T94	0	1	0	0
T96	0	2	0	0
T104	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	8837	0	0
T1	364	1	0	0
T2	15709	106	0	0
T3	566	2	0	0
T4	4557	14	0	0
T5	599	2	0	0
T6	171	1	0	0
T7	569	2	0	0
T8	206	1	0	0
T9	746	2	0	0
T10	7820	52	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	21856	0	0
T1	2924	1	0	0
T2	122376	298	0	0
T3	4527	6	0	0
T4	35957	45	0	0
T5	4811	2	0	0
T6	1383	2	0	0
T7	4566	2	0	0
T8	1650	2	0	0
T9	5980	6	0	0
T10	60315	161	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	21856	0	0
T1	2924	1	0	0
T2	122376	298	0	0
T3	4527	6	0	0
T4	35957	45	0	0
T5	4811	2	0	0
T6	1383	2	0	0
T7	4566	2	0	0
T8	1650	2	0	0
T9	5980	6	0	0
T10	60315	161	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11804359	21856	0	0
T1	2905	1	0	0
T2	98766	298	0	0
T3	4333	6	0	0
T4	31719	45	0	0
T5	4697	2	0	0
T6	1263	2	0	0
T7	4428	2	0	0
T8	1463	2	0	0
T9	5694	6	0	0
T10	47624	161	0	0