Module Definition
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Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T47,T32,T66 Yes T47,T32,T66 INPUT
alert_req_i Yes Yes T50,T51,T52 Yes T50,T51,T52 INPUT
alert_ack_o Yes Yes T50,T51,T52 Yes T50,T51,T52 OUTPUT
alert_state_o Yes Yes T50,T51,T52 Yes T50,T51,T52 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T50,T51,T52 Yes T50,T51,T52 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T50,T51,T52 Yes T50,T51,T52 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T47,T32,T66 Yes T47,T32,T66 INPUT
alert_req_i Yes Yes T63,T64,T65 Yes T63,T64,T65 INPUT
alert_ack_o Yes Yes T63,T64,T65 Yes T63,T64,T65 OUTPUT
alert_state_o Yes Yes T63,T64,T65 Yes T63,T64,T65 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T47,T32,T66 Yes T47,T32,T66 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T47,T32,T66 Yes T47,T32,T66 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T47,T32,T66 Yes T47,T32,T66 INPUT
alert_req_i Yes Yes T50,T51,T52 Yes T50,T51,T52 INPUT
alert_ack_o Yes Yes T50,T51,T52 Yes T50,T51,T52 OUTPUT
alert_state_o Yes Yes T50,T51,T52 Yes T50,T51,T52 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T50,T51,T52 Yes T50,T51,T52 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T50,T51,T52 Yes T50,T51,T52 OUTPUT