Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13248960	13843	0	0
gen_assertions[0].RstEnOn_A	13248960	964	0	0
gen_assertions[0].RstNOff_A	13248960	13843	0	0
gen_assertions[0].RstNOn_A	13248960	964	0	0
gen_assertions[1].RstEnOff_A	52995196	12589	0	0
gen_assertions[1].RstEnOn_A	52995196	927	0	0
gen_assertions[1].RstNOff_A	52995196	12589	0	0
gen_assertions[1].RstNOn_A	52995196	927	0	0
gen_assertions[2].RstEnOff_A	26498943	12619	0	0
gen_assertions[2].RstEnOn_A	26498943	924	0	0
gen_assertions[2].RstNOff_A	26498943	12619	0	0
gen_assertions[2].RstNOn_A	26498943	924	0	0
gen_assertions[3].RstEnOff_A	26498824	12687	0	0
gen_assertions[3].RstEnOn_A	26498824	997	0	0
gen_assertions[3].RstNOff_A	26498824	12687	0	0
gen_assertions[3].RstNOn_A	26498824	997	0	0
gen_assertions[4].RstEnOff_A	1672342	21669	0	0
gen_assertions[4].RstEnOn_A	1672342	1039	0	0
gen_assertions[4].RstNOff_A	1672342	21669	0	0
gen_assertions[4].RstNOn_A	1672342	1039	0	0
gen_assertions[5].RstEnOff_A	13248960	14119	0	0
gen_assertions[5].RstEnOn_A	13248960	1129	0	0
gen_assertions[5].RstNOff_A	13248960	14119	0	0
gen_assertions[5].RstNOn_A	13248960	1129	0	0
gen_assertions[6].RstEnOff_A	13248960	14115	0	0
gen_assertions[6].RstEnOn_A	13248960	1125	0	0
gen_assertions[6].RstNOff_A	13248960	14115	0	0
gen_assertions[6].RstNOn_A	13248960	1125	0	0
gen_assertions[7].RstEnOff_A	13248960	14199	0	0
gen_assertions[7].RstEnOn_A	13248960	1207	0	0
gen_assertions[7].RstNOff_A	13248960	14199	0	0
gen_assertions[7].RstNOn_A	13248960	1207	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	13843	0	0
T1	2924	1	0	0
T2	122376	209	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	5	0	0
T10	60315	116	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	964	0	0
T1	2924	1	0	0
T2	122376	19	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	1	0	0
T10	60315	7	0	0
T11	0	4	0	0
T37	0	8	0	0
T38	0	3	0	0
T48	0	5	0	0
T78	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	13843	0	0
T1	2924	1	0	0
T2	122376	209	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	5	0	0
T10	60315	116	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	964	0	0
T1	2924	1	0	0
T2	122376	19	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	1	0	0
T10	60315	7	0	0
T11	0	4	0	0
T37	0	8	0	0
T38	0	3	0	0
T48	0	5	0	0
T78	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52995196	12589	0	0
T1	11699	4	0	0
T2	489442	186	0	0
T3	18117	4	0	0
T4	143820	28	0	0
T5	19250	0	0	0
T6	5530	1	0	0
T7	18269	0	0	0
T8	6608	1	0	0
T9	23926	4	0	0
T10	241233	104	0	0
T11	0	14	0	0
T20	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52995196	927	0	0
T1	11699	4	0	0
T2	489442	14	0	0
T3	18117	0	0	0
T4	143820	0	0	0
T5	19250	0	0	0
T6	5530	0	0	0
T7	18269	0	0	0
T8	6608	0	0	0
T9	23926	0	0	0
T10	241233	8	0	0
T21	0	1	0	0
T37	0	8	0	0
T38	0	2	0	0
T48	0	7	0	0
T78	0	3	0	0
T79	0	8	0	0
T80	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52995196	12589	0	0
T1	11699	4	0	0
T2	489442	186	0	0
T3	18117	4	0	0
T4	143820	28	0	0
T5	19250	0	0	0
T6	5530	1	0	0
T7	18269	0	0	0
T8	6608	1	0	0
T9	23926	4	0	0
T10	241233	104	0	0
T11	0	14	0	0
T20	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52995196	927	0	0
T1	11699	4	0	0
T2	489442	14	0	0
T3	18117	0	0	0
T4	143820	0	0	0
T5	19250	0	0	0
T6	5530	0	0	0
T7	18269	0	0	0
T8	6608	0	0	0
T9	23926	0	0	0
T10	241233	8	0	0
T21	0	1	0	0
T37	0	8	0	0
T38	0	2	0	0
T48	0	7	0	0
T78	0	3	0	0
T79	0	8	0	0
T80	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498943	12619	0	0
T1	5850	5	0	0
T2	244741	186	0	0
T3	9060	4	0	0
T4	71927	28	0	0
T5	9624	0	0	0
T6	2764	1	0	0
T7	9135	0	0	0
T8	3303	1	0	0
T9	11962	4	0	0
T10	120616	102	0	0
T11	0	14	0	0
T20	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498943	924	0	0
T1	5850	5	0	0
T2	244741	16	0	0
T3	9060	0	0	0
T4	71927	0	0	0
T5	9624	0	0	0
T6	2764	0	0	0
T7	9135	0	0	0
T8	3303	0	0	0
T9	11962	0	0	0
T10	120616	6	0	0
T37	0	5	0	0
T38	0	3	0	0
T48	0	7	0	0
T79	0	7	0	0
T80	0	2	0	0
T81	0	9	0	0
T82	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498943	12619	0	0
T1	5850	5	0	0
T2	244741	186	0	0
T3	9060	4	0	0
T4	71927	28	0	0
T5	9624	0	0	0
T6	2764	1	0	0
T7	9135	0	0	0
T8	3303	1	0	0
T9	11962	4	0	0
T10	120616	102	0	0
T11	0	14	0	0
T20	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498943	924	0	0
T1	5850	5	0	0
T2	244741	16	0	0
T3	9060	0	0	0
T4	71927	0	0	0
T5	9624	0	0	0
T6	2764	0	0	0
T7	9135	0	0	0
T8	3303	0	0	0
T9	11962	0	0	0
T10	120616	6	0	0
T37	0	5	0	0
T38	0	3	0	0
T48	0	7	0	0
T79	0	7	0	0
T80	0	2	0	0
T81	0	9	0	0
T82	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498824	12687	0	0
T1	5849	6	0	0
T2	244720	188	0	0
T3	9056	4	0	0
T4	71934	28	0	0
T5	9624	0	0	0
T6	2764	1	0	0
T7	9134	0	0	0
T8	3304	1	0	0
T9	11961	4	0	0
T10	120606	105	0	0
T11	0	14	0	0
T20	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498824	997	0	0
T1	5849	6	0	0
T2	244720	18	0	0
T3	9056	0	0	0
T4	71934	0	0	0
T5	9624	0	0	0
T6	2764	0	0	0
T7	9134	0	0	0
T8	3304	0	0	0
T9	11961	0	0	0
T10	120606	9	0	0
T37	0	6	0	0
T38	0	6	0	0
T48	0	10	0	0
T79	0	7	0	0
T80	0	5	0	0
T81	0	7	0	0
T83	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498824	12687	0	0
T1	5849	6	0	0
T2	244720	188	0	0
T3	9056	4	0	0
T4	71934	28	0	0
T5	9624	0	0	0
T6	2764	1	0	0
T7	9134	0	0	0
T8	3304	1	0	0
T9	11961	4	0	0
T10	120606	105	0	0
T11	0	14	0	0
T20	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26498824	997	0	0
T1	5849	6	0	0
T2	244720	18	0	0
T3	9056	0	0	0
T4	71934	0	0	0
T5	9624	0	0	0
T6	2764	0	0	0
T7	9134	0	0	0
T8	3304	0	0	0
T9	11961	0	0	0
T10	120606	9	0	0
T37	0	6	0	0
T38	0	6	0	0
T48	0	10	0	0
T79	0	7	0	0
T80	0	5	0	0
T81	0	7	0	0
T83	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	21669	0	0
T1	364	7	0	0
T2	15709	310	0	0
T3	566	6	0	0
T4	4557	45	0	0
T5	599	2	0	0
T6	171	2	0	0
T7	569	2	0	0
T8	206	2	0	0
T9	746	7	0	0
T10	7820	159	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	1039	0	0
T1	364	6	0	0
T2	15709	18	0	0
T3	566	0	0	0
T4	4557	0	0	0
T5	599	0	0	0
T6	171	0	0	0
T7	569	0	0	0
T8	206	0	0	0
T9	746	1	0	0
T10	7820	7	0	0
T37	0	5	0	0
T38	0	5	0	0
T48	0	11	0	0
T79	0	10	0	0
T80	0	7	0	0
T84	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	21669	0	0
T1	364	7	0	0
T2	15709	310	0	0
T3	566	6	0	0
T4	4557	45	0	0
T5	599	2	0	0
T6	171	2	0	0
T7	569	2	0	0
T8	206	2	0	0
T9	746	7	0	0
T10	7820	159	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1672342	1039	0	0
T1	364	6	0	0
T2	15709	18	0	0
T3	566	0	0	0
T4	4557	0	0	0
T5	599	0	0	0
T6	171	0	0	0
T7	569	0	0	0
T8	206	0	0	0
T9	746	1	0	0
T10	7820	7	0	0
T37	0	5	0	0
T38	0	5	0	0
T48	0	11	0	0
T79	0	10	0	0
T80	0	7	0	0
T84	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	14119	0	0
T1	2924	7	0	0
T2	122376	210	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	5	0	0
T10	60315	115	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	1129	0	0
T1	2924	7	0	0
T2	122376	20	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	0	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	1	0	0
T10	60315	6	0	0
T21	0	1	0	0
T37	0	9	0	0
T38	0	7	0	0
T48	0	13	0	0
T79	0	13	0	0
T84	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	14119	0	0
T1	2924	7	0	0
T2	122376	210	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	5	0	0
T10	60315	115	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	1129	0	0
T1	2924	7	0	0
T2	122376	20	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	0	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	1	0	0
T10	60315	6	0	0
T21	0	1	0	0
T37	0	9	0	0
T38	0	7	0	0
T48	0	13	0	0
T79	0	13	0	0
T84	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	14115	0	0
T1	2924	9	0	0
T2	122376	208	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	4	0	0
T10	60315	116	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	1125	0	0
T1	2924	9	0	0
T2	122376	18	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	0	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	0	0	0
T10	60315	7	0	0
T37	0	8	0	0
T38	0	9	0	0
T48	0	14	0	0
T79	0	8	0	0
T80	0	6	0	0
T81	0	6	0	0
T82	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	14115	0	0
T1	2924	9	0	0
T2	122376	208	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	4	0	0
T10	60315	116	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	1125	0	0
T1	2924	9	0	0
T2	122376	18	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	0	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	0	0	0
T10	60315	7	0	0
T37	0	8	0	0
T38	0	9	0	0
T48	0	14	0	0
T79	0	8	0	0
T80	0	6	0	0
T81	0	6	0	0
T82	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	14199	0	0
T1	2924	9	0	0
T2	122376	206	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	4	0	0
T10	60315	116	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	1207	0	0
T1	2924	9	0	0
T2	122376	16	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	0	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	0	0	0
T10	60315	7	0	0
T37	0	8	0	0
T38	0	10	0	0
T48	0	15	0	0
T79	0	13	0	0
T80	0	9	0	0
T81	0	7	0	0
T85	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	14199	0	0
T1	2924	9	0	0
T2	122376	206	0	0
T3	4527	4	0	0
T4	35957	31	0	0
T5	4811	0	0	0
T6	1383	1	0	0
T7	4566	0	0	0
T8	1650	1	0	0
T9	5980	4	0	0
T10	60315	116	0	0
T11	0	15	0	0
T20	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13248960	1207	0	0
T1	2924	9	0	0
T2	122376	16	0	0
T3	4527	0	0	0
T4	35957	0	0	0
T5	4811	0	0	0
T6	1383	0	0	0
T7	4566	0	0	0
T8	1650	0	0	0
T9	5980	0	0	0
T10	60315	7	0	0
T37	0	8	0	0
T38	0	10	0	0
T48	0	15	0	0
T79	0	13	0	0
T80	0	9	0	0
T81	0	7	0	0
T85	0	1	0	0