Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12626671	7107	0	0
alert_regwen_rd_A	12626671	5491	0	0
cpu_regwen_rd_A	12626671	5264	0	0
sw_rst_ctrl_n_0_rd_A	12626671	11555	0	0
sw_rst_ctrl_n_1_rd_A	12626671	11319	0	0
sw_rst_ctrl_n_2_rd_A	12626671	11510	0	0
sw_rst_ctrl_n_3_rd_A	12626671	11328	0	0
sw_rst_ctrl_n_4_rd_A	12626671	11490	0	0
sw_rst_ctrl_n_5_rd_A	12626671	11621	0	0
sw_rst_ctrl_n_6_rd_A	12626671	11783	0	0
sw_rst_ctrl_n_7_rd_A	12626671	11446	0	0
sw_rst_regwen_0_rd_A	12626671	6089	0	0
sw_rst_regwen_1_rd_A	12626671	6268	0	0
sw_rst_regwen_2_rd_A	12626671	6167	0	0
sw_rst_regwen_3_rd_A	12626671	6040	0	0
sw_rst_regwen_4_rd_A	12626671	6181	0	0
sw_rst_regwen_5_rd_A	12626671	6196	0	0
sw_rst_regwen_6_rd_A	12626671	6031	0	0
sw_rst_regwen_7_rd_A	12626671	6252	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	7107	0	0
T55	20434	2	0	0
T57	3261	10	0	0
T58	4522	91	0	0
T59	10725	2	0	0
T61	2213	179	0	0
T62	20580	1	0	0
T86	2489	1	0	0
T87	3096	12	0	0
T88	2768	13	0	0
T89	11620	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	5491	0	0
T4	31719	54	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	0	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T39	0	71	0	0
T98	0	239	0	0
T99	0	244	0	0
T100	0	242	0	0
T125	0	40	0	0
T126	0	46	0	0
T127	0	264	0	0
T128	0	11	0	0
T129	0	26	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	5264	0	0
T4	31719	37	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	0	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T39	0	64	0	0
T98	0	235	0	0
T99	0	275	0	0
T100	0	270	0	0
T125	0	38	0	0
T126	0	42	0	0
T127	0	292	0	0
T128	0	14	0	0
T129	0	28	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11555	0	0
T4	31719	53	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	1	0	0
T9	5694	17	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	160	0	0
T39	0	72	0	0
T48	0	185	0	0
T82	0	186	0	0
T84	0	17	0	0
T130	0	59	0	0
T131	0	16	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11319	0	0
T4	31719	59	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	4	0	0
T9	5694	19	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	174	0	0
T39	0	94	0	0
T48	0	212	0	0
T84	0	13	0	0
T85	0	10	0	0
T130	0	36	0	0
T131	0	14	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11510	0	0
T4	31719	37	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	4	0	0
T9	5694	16	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	157	0	0
T39	0	89	0	0
T48	0	207	0	0
T84	0	20	0	0
T85	0	5	0	0
T130	0	70	0	0
T131	0	16	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11328	0	0
T4	31719	45	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	4	0	0
T9	5694	6	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	128	0	0
T39	0	77	0	0
T48	0	207	0	0
T84	0	10	0	0
T85	0	11	0	0
T130	0	55	0	0
T131	0	14	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11490	0	0
T4	31719	51	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	5	0	0
T9	5694	3	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	154	0	0
T39	0	89	0	0
T48	0	193	0	0
T84	0	12	0	0
T85	0	4	0	0
T130	0	45	0	0
T131	0	10	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11621	0	0
T4	31719	29	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	1	0	0
T9	5694	21	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	151	0	0
T39	0	72	0	0
T48	0	228	0	0
T84	0	14	0	0
T85	0	2	0	0
T130	0	65	0	0
T131	0	16	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11783	0	0
T4	31719	58	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	3	0	0
T9	5694	13	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	132	0	0
T39	0	86	0	0
T48	0	194	0	0
T84	0	15	0	0
T85	0	3	0	0
T130	0	43	0	0
T131	0	12	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	11446	0	0
T4	31719	47	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	2	0	0
T9	5694	9	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	140	0	0
T39	0	59	0	0
T48	0	156	0	0
T84	0	12	0	0
T85	0	5	0	0
T130	0	79	0	0
T131	0	19	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6089	0	0
T4	31719	24	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	8	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	25	0	0
T39	0	77	0	0
T48	0	32	0	0
T82	0	38	0	0
T84	0	10	0	0
T85	0	6	0	0
T98	0	208	0	0
T131	0	5	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6268	0	0
T4	31719	53	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	7	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	23	0	0
T39	0	104	0	0
T48	0	24	0	0
T82	0	52	0	0
T84	0	3	0	0
T85	0	8	0	0
T98	0	264	0	0
T131	0	11	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6167	0	0
T4	31719	33	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	4	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	38	0	0
T39	0	102	0	0
T48	0	24	0	0
T82	0	22	0	0
T84	0	4	0	0
T98	0	229	0	0
T131	0	8	0	0
T132	0	9	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6040	0	0
T4	31719	36	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	11	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	22	0	0
T39	0	82	0	0
T48	0	38	0	0
T82	0	37	0	0
T84	0	4	0	0
T85	0	2	0	0
T98	0	252	0	0
T131	0	8	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6181	0	0
T4	31719	46	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	13	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	41	0	0
T39	0	100	0	0
T48	0	36	0	0
T82	0	18	0	0
T84	0	7	0	0
T85	0	1	0	0
T98	0	252	0	0
T131	0	1	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6196	0	0
T4	31719	58	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	5	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	39	0	0
T39	0	98	0	0
T48	0	27	0	0
T82	0	33	0	0
T84	0	10	0	0
T85	0	8	0	0
T98	0	271	0	0
T131	0	8	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6031	0	0
T4	31719	32	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	11	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	32	0	0
T39	0	71	0	0
T48	0	27	0	0
T82	0	36	0	0
T84	0	7	0	0
T85	0	1	0	0
T98	0	247	0	0
T131	0	3	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12626671	6252	0	0
T4	31719	51	0	0
T5	4697	0	0	0
T6	1263	0	0	0
T7	4428	0	0	0
T8	1463	0	0	0
T9	5694	4	0	0
T10	47624	0	0	0
T11	3961	0	0	0
T12	3997	0	0	0
T20	4177	0	0	0
T38	0	26	0	0
T39	0	71	0	0
T48	0	34	0	0
T82	0	53	0	0
T84	0	9	0	0
T85	0	6	0	0
T98	0	231	0	0
T131	0	13	0	0