Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	664214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

400553

1

T2

76

T4

7675

T5

105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	567991	1			T2	99		T4	11480		T5	144
values[0x0]	248071	1			T2	61		T4	4733		T5	74
values[0x1]	248705	1			T2	52		T4	4712		T5	76

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	556650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

508117

1

T2

100

T4

9818

T5

136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5042	1			T4	44		T6	2		T23	13
valid_sources[0x01]	3103	1			T4	65		T11	2		T23	17
valid_sources[0x02]	4045	1			T4	64		T11	33		T23	16
valid_sources[0x03]	3628	1			T4	76		T23	5		T25	2
valid_sources[0x04]	3999	1			T4	102		T6	1		T11	10
valid_sources[0x05]	3718	1			T4	66		T11	13		T23	10
valid_sources[0x06]	7640	1			T4	68		T11	18		T23	18
valid_sources[0x07]	3568	1			T2	1		T4	78		T11	1
valid_sources[0x08]	4026	1			T4	92		T11	62		T23	17
valid_sources[0x09]	7912	1			T2	3		T4	87		T5	2
valid_sources[0x0a]	4435	1			T4	68		T5	10		T11	54
valid_sources[0x0b]	3278	1			T2	2		T4	83		T11	4
valid_sources[0x0c]	4118	1			T2	4		T4	72		T6	9
valid_sources[0x0d]	7780	1			T4	73		T5	2		T11	5
valid_sources[0x0e]	3085	1			T2	3		T4	108		T11	9
valid_sources[0x0f]	3703	1			T4	89		T11	6		T12	4
valid_sources[0x10]	3567	1			T4	108		T5	1		T11	13
valid_sources[0x11]	3977	1			T4	81		T5	2		T6	1
valid_sources[0x12]	3599	1			T4	94		T11	13		T12	14
valid_sources[0x13]	5724	1			T2	3		T4	85		T6	8
valid_sources[0x14]	3573	1			T4	63		T12	2		T23	24
valid_sources[0x15]	3904	1			T2	2		T4	82		T11	23
valid_sources[0x16]	3816	1			T2	1		T4	115		T11	41
valid_sources[0x17]	4128	1			T2	1		T4	103		T5	9
valid_sources[0x18]	3640	1			T4	98		T23	19		T24	4
valid_sources[0x19]	3453	1			T4	91		T11	2		T12	7
valid_sources[0x1a]	3671	1			T2	5		T4	73		T11	2
valid_sources[0x1b]	3004	1			T2	1		T4	56		T5	3
valid_sources[0x1c]	4479	1			T2	1		T4	75		T11	20
valid_sources[0x1d]	3091	1			T2	1		T4	55		T23	18
valid_sources[0x1e]	4917	1			T2	1		T4	70		T11	12
valid_sources[0x1f]	3711	1			T4	50		T11	21		T12	4
valid_sources[0x20]	3777	1			T2	3		T4	98		T5	2
valid_sources[0x21]	3607	1			T2	1		T4	71		T5	1
valid_sources[0x22]	7141	1			T4	101		T5	1		T11	24
valid_sources[0x23]	7709	1			T2	1		T4	77		T5	3
valid_sources[0x24]	3805	1			T4	86		T11	29		T12	3
valid_sources[0x25]	3333	1			T2	1		T4	77		T11	37
valid_sources[0x26]	4071	1			T4	71		T11	9		T23	14
valid_sources[0x27]	4140	1			T2	1		T4	94		T5	6
valid_sources[0x28]	3892	1			T2	2		T4	116		T12	3
valid_sources[0x29]	7067	1			T2	2		T4	83		T6	5
valid_sources[0x2a]	4429	1			T2	4		T4	119		T5	2
valid_sources[0x2b]	4742	1			T4	77		T5	2		T11	15
valid_sources[0x2c]	3965	1			T2	2		T4	116		T5	5
valid_sources[0x2d]	4338	1			T4	73		T6	6		T12	4
valid_sources[0x2e]	3410	1			T4	94		T5	4		T11	12
valid_sources[0x2f]	3873	1			T4	72		T5	9		T7	1080
valid_sources[0x30]	5613	1			T2	1		T4	92		T11	8
valid_sources[0x31]	4482	1			T4	79		T11	10		T23	11
valid_sources[0x32]	4242	1			T4	34		T6	3		T12	3
valid_sources[0x33]	3443	1			T2	2		T4	83		T5	12
valid_sources[0x34]	3086	1			T2	1		T4	86		T5	5
valid_sources[0x35]	3857	1			T2	5		T4	68		T11	34
valid_sources[0x36]	5359	1			T2	2		T4	67		T11	31
valid_sources[0x37]	3453	1			T4	60		T11	7		T23	12
valid_sources[0x38]	3794	1			T4	60		T11	20		T23	10
valid_sources[0x39]	4347	1			T2	1		T4	111		T11	8
valid_sources[0x3a]	3444	1			T2	1		T4	78		T23	17
valid_sources[0x3b]	4522	1			T4	68		T23	15		T24	6
valid_sources[0x3c]	6951	1			T4	62		T5	2		T11	6
valid_sources[0x3d]	3680	1			T4	100		T5	2		T11	15
valid_sources[0x3e]	5677	1			T4	63		T11	1		T23	21
valid_sources[0x3f]	4970	1			T2	1		T4	98		T11	14
valid_sources[0x40]	5159	1			T2	1		T4	88		T11	31
valid_sources[0x41]	4658	1			T2	3		T4	85		T6	1
valid_sources[0x42]	5030	1			T4	63		T11	32		T12	5
valid_sources[0x43]	3930	1			T2	3		T4	51		T11	9
valid_sources[0x44]	4701	1			T4	66		T6	6		T11	11
valid_sources[0x45]	3905	1			T2	1		T4	133		T5	2
valid_sources[0x46]	5918	1			T4	70		T11	4		T12	5
valid_sources[0x47]	3490	1			T4	78		T11	11		T12	3
valid_sources[0x48]	3860	1			T2	4		T4	80		T11	1
valid_sources[0x49]	3360	1			T4	61		T23	13		T24	1
valid_sources[0x4a]	3754	1			T4	70		T6	12		T11	11
valid_sources[0x4b]	6571	1			T4	67		T11	29		T23	11
valid_sources[0x4c]	4206	1			T4	99		T6	18		T11	9
valid_sources[0x4d]	3406	1			T4	58		T5	6		T11	19
valid_sources[0x4e]	4091	1			T2	1		T4	110		T5	1
valid_sources[0x4f]	3534	1			T2	4		T4	44		T11	2
valid_sources[0x50]	4513	1			T2	1		T4	59		T11	13
valid_sources[0x51]	4469	1			T4	74		T5	2		T11	7
valid_sources[0x52]	4403	1			T4	102		T11	11		T12	4
valid_sources[0x53]	6406	1			T4	85		T11	1		T23	10
valid_sources[0x54]	4277	1			T2	1		T4	62		T5	3
valid_sources[0x55]	3179	1			T4	70		T5	3		T11	7
valid_sources[0x56]	3555	1			T2	1		T4	125		T11	2
valid_sources[0x57]	3889	1			T2	4		T4	67		T11	8
valid_sources[0x58]	3805	1			T4	79		T11	5		T23	20
valid_sources[0x59]	4147	1			T2	1		T4	41		T11	10
valid_sources[0x5a]	4000	1			T2	3		T4	81		T11	13
valid_sources[0x5b]	3790	1			T2	2		T4	94		T11	25
valid_sources[0x5c]	3643	1			T4	66		T11	10		T23	9
valid_sources[0x5d]	3412	1			T2	5		T4	58		T11	21
valid_sources[0x5e]	3695	1			T4	86		T11	12		T23	10
valid_sources[0x5f]	3974	1			T2	1		T4	72		T11	5
valid_sources[0x60]	4073	1			T2	3		T4	87		T11	41
valid_sources[0x61]	3919	1			T4	101		T11	1		T23	16
valid_sources[0x62]	3291	1			T2	1		T4	91		T11	4
valid_sources[0x63]	5012	1			T4	78		T5	4		T11	1
valid_sources[0x64]	3519	1			T2	1		T4	85		T5	6
valid_sources[0x65]	4292	1			T4	110		T5	2		T6	5
valid_sources[0x66]	3831	1			T4	113		T6	16		T11	33
valid_sources[0x67]	4838	1			T4	74		T11	8		T23	15
valid_sources[0x68]	5902	1			T4	119		T11	2		T23	16
valid_sources[0x69]	4052	1			T2	1		T4	106		T5	6
valid_sources[0x6a]	3617	1			T4	65		T5	1		T11	5
valid_sources[0x6b]	4017	1			T4	94		T11	17		T12	9
valid_sources[0x6c]	3536	1			T2	2		T4	72		T11	29
valid_sources[0x6d]	3928	1			T2	2		T4	86		T11	3
valid_sources[0x6e]	4402	1			T4	71		T5	5		T11	13
valid_sources[0x6f]	3309	1			T2	1		T4	76		T5	1
valid_sources[0x70]	4783	1			T4	83		T6	4		T11	12
valid_sources[0x71]	4140	1			T2	1		T4	47		T9	212
valid_sources[0x72]	3129	1			T4	82		T11	12		T12	1
valid_sources[0x73]	2806	1			T2	1		T4	65		T5	3
valid_sources[0x74]	3913	1			T4	83		T6	9		T11	12
valid_sources[0x75]	3085	1			T4	75		T11	13		T23	7
valid_sources[0x76]	4334	1			T2	4		T4	95		T11	5
valid_sources[0x77]	6371	1			T2	2		T4	87		T11	3
valid_sources[0x78]	4293	1			T4	45		T23	11		T24	3
valid_sources[0x79]	3094	1			T2	3		T4	63		T11	1
valid_sources[0x7a]	4161	1			T4	50		T5	3		T11	4
valid_sources[0x7b]	3884	1			T2	1		T4	64		T23	16
valid_sources[0x7c]	3224	1			T2	4		T4	118		T5	2
valid_sources[0x7d]	3257	1			T2	1		T4	92		T11	5
valid_sources[0x7e]	3706	1			T2	1		T4	99		T11	5
valid_sources[0x7f]	3622	1			T4	92		T5	1		T11	3
valid_sources[0x80]	4222	1			T2	1		T4	63		T11	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

266680

1

T2

46

T4

5363

T5

68

values[0x0]

all_enables

biggest_size

87148

1

T2

22

T4

1547

T5

25

values[0x1]

all_enables

biggest_size

46725

1

T2

8

T4

765

T5

12