Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T4,T11,T43
1	0	Covered	T4,T11,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T4,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	58538067	9314	0	0
CascadeEffAonToRstPorAboveRise_A	58538067	9314	0	0
CascadeEffAonToRstPorIoAboveFall_A	56194689	9314	0	0
CascadeEffAonToRstPorIoAboveRise_A	56194689	9314	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	28098214	9314	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	28098214	9314	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14048957	9314	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14048957	9314	0	0
CascadeEffAonToRstPorUcbAboveFall_A	28098204	9314	0	0
CascadeEffAonToRstPorUcbAboveRise_A	28098204	9314	0	0
CascadeLcToLcAboveFall_A	58538067	23638	0	0
CascadeLcToLcAboveRise_A	58538067	23638	0	0
CascadeLcToLcAonAboveFall_A	1774719	23638	0	0
CascadeLcToLcAonAboveRise_A	1774719	23638	0	0
CascadeLcToLcShadowedAboveFall_A	58538067	23638	0	0
CascadeLcToLcShadowedAboveRise_A	58538067	23638	0	0
CascadePorToAonAboveFall_A	1774719	7365	0	0
CascadeSysToSysAboveFall_A	58538067	23638	0	0
CascadeSysToSysAboveRise_A	58538067	23638	0	0
ScanRstToAonRise_A	1774719	221	0	0
StablePorToAonRise_A	1774719	9314	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12405792	23638	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12405792	23638	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12405792	23638	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12405792	23638	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14048957	23638	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14048957	23638	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12405792	23638	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12405792	23638	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12405792	23638	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12405792	23638	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	9314	0	0
T1	24301	8	0	0
T2	14447	2	0	0
T3	24289	8	0	0
T4	652359	129	0	0
T5	21094	1	0	0
T6	21285	1	0	0
T7	15340	1	0	0
T8	9817	2	0	0
T9	14360	2	0	0
T10	17099	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	9314	0	0
T1	24301	8	0	0
T2	14447	2	0	0
T3	24289	8	0	0
T4	652359	129	0	0
T5	21094	1	0	0
T6	21285	1	0	0
T7	15340	1	0	0
T8	9817	2	0	0
T9	14360	2	0	0
T10	17099	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56194689	9314	0	0
T1	23330	8	0	0
T2	13872	2	0	0
T3	23326	8	0	0
T4	626287	129	0	0
T5	20250	1	0	0
T6	20433	1	0	0
T7	14727	1	0	0
T8	9428	2	0	0
T9	13781	2	0	0
T10	16414	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56194689	9314	0	0
T1	23330	8	0	0
T2	13872	2	0	0
T3	23326	8	0	0
T4	626287	129	0	0
T5	20250	1	0	0
T6	20433	1	0	0
T7	14727	1	0	0
T8	9428	2	0	0
T9	13781	2	0	0
T10	16414	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098214	9314	0	0
T1	11657	8	0	0
T2	6934	2	0	0
T3	11665	8	0	0
T4	313153	129	0	0
T5	10124	1	0	0
T6	10217	1	0	0
T7	7363	1	0	0
T8	4709	2	0	0
T9	6892	2	0	0
T10	8207	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098214	9314	0	0
T1	11657	8	0	0
T2	6934	2	0	0
T3	11665	8	0	0
T4	313153	129	0	0
T5	10124	1	0	0
T6	10217	1	0	0
T7	7363	1	0	0
T8	4709	2	0	0
T9	6892	2	0	0
T10	8207	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	9314	0	0
T1	5828	8	0	0
T2	3466	2	0	0
T3	5833	8	0	0
T4	156591	129	0	0
T5	5061	1	0	0
T6	5107	1	0	0
T7	3680	1	0	0
T8	2355	2	0	0
T9	3444	2	0	0
T10	4102	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	9314	0	0
T1	5828	8	0	0
T2	3466	2	0	0
T3	5833	8	0	0
T4	156591	129	0	0
T5	5061	1	0	0
T6	5107	1	0	0
T7	3680	1	0	0
T8	2355	2	0	0
T9	3444	2	0	0
T10	4102	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098204	9314	0	0
T1	11656	8	0	0
T2	6932	2	0	0
T3	11657	8	0	0
T4	313159	129	0	0
T5	10124	1	0	0
T6	10217	1	0	0
T7	7363	1	0	0
T8	4711	2	0	0
T9	6892	2	0	0
T10	8207	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098204	9314	0	0
T1	11656	8	0	0
T2	6932	2	0	0
T3	11657	8	0	0
T4	313159	129	0	0
T5	10124	1	0	0
T6	10217	1	0	0
T7	7363	1	0	0
T8	4711	2	0	0
T9	6892	2	0	0
T10	8207	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	23638	0	0
T1	24301	8	0	0
T2	14447	6	0	0
T3	24289	8	0	0
T4	652359	418	0	0
T5	21094	17	0	0
T6	21285	14	0	0
T7	15340	1	0	0
T8	9817	6	0	0
T9	14360	6	0	0
T10	17099	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	23638	0	0
T1	24301	8	0	0
T2	14447	6	0	0
T3	24289	8	0	0
T4	652359	418	0	0
T5	21094	17	0	0
T6	21285	14	0	0
T7	15340	1	0	0
T8	9817	6	0	0
T9	14360	6	0	0
T10	17099	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	23638	0	0
T1	730	8	0	0
T2	432	6	0	0
T3	730	8	0	0
T4	20114	418	0	0
T5	632	17	0	0
T6	637	14	0	0
T7	459	1	0	0
T8	293	6	0	0
T9	430	6	0	0
T10	512	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	23638	0	0
T1	730	8	0	0
T2	432	6	0	0
T3	730	8	0	0
T4	20114	418	0	0
T5	632	17	0	0
T6	637	14	0	0
T7	459	1	0	0
T8	293	6	0	0
T9	430	6	0	0
T10	512	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	23638	0	0
T1	24301	8	0	0
T2	14447	6	0	0
T3	24289	8	0	0
T4	652359	418	0	0
T5	21094	17	0	0
T6	21285	14	0	0
T7	15340	1	0	0
T8	9817	6	0	0
T9	14360	6	0	0
T10	17099	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	23638	0	0
T1	24301	8	0	0
T2	14447	6	0	0
T3	24289	8	0	0
T4	652359	418	0	0
T5	21094	17	0	0
T6	21285	14	0	0
T7	15340	1	0	0
T8	9817	6	0	0
T9	14360	6	0	0
T10	17099	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	7365	0	0
T1	730	8	0	0
T2	432	1	0	0
T3	730	8	0	0
T4	20114	65	0	0
T5	632	1	0	0
T6	637	1	0	0
T7	459	1	0	0
T8	293	1	0	0
T9	430	1	0	0
T10	512	14	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	23638	0	0
T1	24301	8	0	0
T2	14447	6	0	0
T3	24289	8	0	0
T4	652359	418	0	0
T5	21094	17	0	0
T6	21285	14	0	0
T7	15340	1	0	0
T8	9817	6	0	0
T9	14360	6	0	0
T10	17099	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58538067	23638	0	0
T1	24301	8	0	0
T2	14447	6	0	0
T3	24289	8	0	0
T4	652359	418	0	0
T5	21094	17	0	0
T6	21285	14	0	0
T7	15340	1	0	0
T8	9817	6	0	0
T9	14360	6	0	0
T10	17099	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	221	0	0
T4	20114	7	0	0
T5	632	0	0	0
T6	637	0	0	0
T7	459	0	0	0
T8	293	0	0	0
T9	430	0	0	0
T10	512	0	0	0
T11	2882	1	0	0
T12	373	0	0	0
T13	5640	0	0	0
T43	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T79	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T126	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	9314	0	0
T1	730	8	0	0
T2	432	2	0	0
T3	730	8	0	0
T4	20114	129	0	0
T5	632	1	0	0
T6	637	1	0	0
T7	459	1	0	0
T8	293	2	0	0
T9	430	2	0	0
T10	512	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	23638	0	0
T1	5828	8	0	0
T2	3466	6	0	0
T3	5833	8	0	0
T4	156591	418	0	0
T5	5061	17	0	0
T6	5107	14	0	0
T7	3680	1	0	0
T8	2355	6	0	0
T9	3444	6	0	0
T10	4102	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	23638	0	0
T1	5828	8	0	0
T2	3466	6	0	0
T3	5833	8	0	0
T4	156591	418	0	0
T5	5061	17	0	0
T6	5107	14	0	0
T7	3680	1	0	0
T8	2355	6	0	0
T9	3444	6	0	0
T10	4102	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12405792	23638	0	0
T1	5284	8	0	0
T2	3132	6	0	0
T3	5286	8	0	0
T4	121190	418	0	0
T5	3947	17	0	0
T6	4305	14	0	0
T7	3662	1	0	0
T8	2115	6	0	0
T9	3300	6	0	0
T10	4012	2	0	0