Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T24
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14048957	15198	0	0
gen_assertions[0].RstEnOn_A	14048957	1087	0	0
gen_assertions[0].RstNOff_A	14048957	15198	0	0
gen_assertions[0].RstNOn_A	14048957	1087	0	0
gen_assertions[1].RstEnOff_A	56194689	13801	0	0
gen_assertions[1].RstEnOn_A	56194689	1051	0	0
gen_assertions[1].RstNOff_A	56194689	13801	0	0
gen_assertions[1].RstNOn_A	56194689	1051	0	0
gen_assertions[2].RstEnOff_A	28098214	13825	0	0
gen_assertions[2].RstEnOn_A	28098214	986	0	0
gen_assertions[2].RstNOff_A	28098214	13825	0	0
gen_assertions[2].RstNOn_A	28098214	986	0	0
gen_assertions[3].RstEnOff_A	28098204	13887	0	0
gen_assertions[3].RstEnOn_A	28098204	1047	0	0
gen_assertions[3].RstNOff_A	28098204	13887	0	0
gen_assertions[3].RstNOn_A	28098204	1047	0	0
gen_assertions[4].RstEnOff_A	1774719	23288	0	0
gen_assertions[4].RstEnOn_A	1774719	1077	0	0
gen_assertions[4].RstNOff_A	1774719	23288	0	0
gen_assertions[4].RstNOn_A	1774719	1077	0	0
gen_assertions[5].RstEnOff_A	14048957	15434	0	0
gen_assertions[5].RstEnOn_A	14048957	1146	0	0
gen_assertions[5].RstNOff_A	14048957	15434	0	0
gen_assertions[5].RstNOn_A	14048957	1146	0	0
gen_assertions[6].RstEnOff_A	14048957	15471	0	0
gen_assertions[6].RstEnOn_A	14048957	1186	0	0
gen_assertions[6].RstNOff_A	14048957	15471	0	0
gen_assertions[6].RstNOn_A	14048957	1186	0	0
gen_assertions[7].RstEnOff_A	14048957	15537	0	0
gen_assertions[7].RstEnOn_A	14048957	1240	0	0
gen_assertions[7].RstNOff_A	14048957	15537	0	0
gen_assertions[7].RstNOn_A	14048957	1240	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15198	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	5	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	5	0	0
T13	0	75	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1087	0	0
T4	156591	8	0	0
T5	5061	1	0	0
T6	5107	6	0	0
T7	3680	5	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	1	0	0
T13	45010	0	0	0
T24	0	5	0	0
T25	0	4	0	0
T26	0	1	0	0
T38	0	3	0	0
T43	0	7	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15198	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	5	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	5	0	0
T13	0	75	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1087	0	0
T4	156591	8	0	0
T5	5061	1	0	0
T6	5107	6	0	0
T7	3680	5	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	1	0	0
T13	45010	0	0	0
T24	0	5	0	0
T25	0	4	0	0
T26	0	1	0	0
T38	0	3	0	0
T43	0	7	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56194689	13801	0	0
T2	13872	4	0	0
T3	23326	0	0	0
T4	626287	260	0	0
T5	20250	13	0	0
T6	20433	11	0	0
T7	14727	7	0	0
T8	9428	4	0	0
T9	13781	4	0	0
T10	16414	0	0	0
T11	89450	41	0	0
T12	0	4	0	0
T13	0	65	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56194689	1051	0	0
T4	626287	9	0	0
T5	20250	0	0	0
T6	20433	0	0	0
T7	14727	7	0	0
T8	9428	0	0	0
T9	13781	0	0	0
T10	16414	0	0	0
T11	89450	0	0	0
T12	11990	0	0	0
T13	180024	0	0	0
T24	0	6	0	0
T25	0	5	0	0
T26	0	4	0	0
T38	0	6	0	0
T43	0	9	0	0
T76	0	9	0	0
T77	0	3	0	0
T78	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56194689	13801	0	0
T2	13872	4	0	0
T3	23326	0	0	0
T4	626287	260	0	0
T5	20250	13	0	0
T6	20433	11	0	0
T7	14727	7	0	0
T8	9428	4	0	0
T9	13781	4	0	0
T10	16414	0	0	0
T11	89450	41	0	0
T12	0	4	0	0
T13	0	65	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56194689	1051	0	0
T4	626287	9	0	0
T5	20250	0	0	0
T6	20433	0	0	0
T7	14727	7	0	0
T8	9428	0	0	0
T9	13781	0	0	0
T10	16414	0	0	0
T11	89450	0	0	0
T12	11990	0	0	0
T13	180024	0	0	0
T24	0	6	0	0
T25	0	5	0	0
T26	0	4	0	0
T38	0	6	0	0
T43	0	9	0	0
T76	0	9	0	0
T77	0	3	0	0
T78	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098214	13825	0	0
T2	6934	4	0	0
T3	11665	0	0	0
T4	313153	260	0	0
T5	10124	13	0	0
T6	10217	11	0	0
T7	7363	7	0	0
T8	4709	4	0	0
T9	6892	4	0	0
T10	8207	0	0	0
T11	44736	41	0	0
T12	0	4	0	0
T13	0	65	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098214	986	0	0
T4	313153	8	0	0
T5	10124	0	0	0
T6	10217	0	0	0
T7	7363	7	0	0
T8	4709	0	0	0
T9	6892	0	0	0
T10	8207	0	0	0
T11	44736	0	0	0
T12	5994	0	0	0
T13	90003	0	0	0
T24	0	7	0	0
T25	0	8	0	0
T26	0	4	0	0
T38	0	5	0	0
T43	0	7	0	0
T53	0	1	0	0
T76	0	1	0	0
T77	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098214	13825	0	0
T2	6934	4	0	0
T3	11665	0	0	0
T4	313153	260	0	0
T5	10124	13	0	0
T6	10217	11	0	0
T7	7363	7	0	0
T8	4709	4	0	0
T9	6892	4	0	0
T10	8207	0	0	0
T11	44736	41	0	0
T12	0	4	0	0
T13	0	65	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098214	986	0	0
T4	313153	8	0	0
T5	10124	0	0	0
T6	10217	0	0	0
T7	7363	7	0	0
T8	4709	0	0	0
T9	6892	0	0	0
T10	8207	0	0	0
T11	44736	0	0	0
T12	5994	0	0	0
T13	90003	0	0	0
T24	0	7	0	0
T25	0	8	0	0
T26	0	4	0	0
T38	0	5	0	0
T43	0	7	0	0
T53	0	1	0	0
T76	0	1	0	0
T77	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098204	13887	0	0
T2	6932	4	0	0
T3	11657	0	0	0
T4	313159	259	0	0
T5	10124	13	0	0
T6	10217	11	0	0
T7	7363	9	0	0
T8	4711	4	0	0
T9	6892	4	0	0
T10	8207	0	0	0
T11	44747	41	0	0
T12	0	4	0	0
T13	0	65	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098204	1047	0	0
T4	313159	8	0	0
T5	10124	0	0	0
T6	10217	0	0	0
T7	7363	9	0	0
T8	4711	0	0	0
T9	6892	0	0	0
T10	8207	0	0	0
T11	44747	0	0	0
T12	5995	0	0	0
T13	90012	0	0	0
T24	0	7	0	0
T25	0	8	0	0
T26	0	6	0	0
T38	0	8	0	0
T43	0	8	0	0
T53	0	1	0	0
T77	0	3	0	0
T79	0	25	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098204	13887	0	0
T2	6932	4	0	0
T3	11657	0	0	0
T4	313159	259	0	0
T5	10124	13	0	0
T6	10217	11	0	0
T7	7363	9	0	0
T8	4711	4	0	0
T9	6892	4	0	0
T10	8207	0	0	0
T11	44747	41	0	0
T12	0	4	0	0
T13	0	65	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28098204	1047	0	0
T4	313159	8	0	0
T5	10124	0	0	0
T6	10217	0	0	0
T7	7363	9	0	0
T8	4711	0	0	0
T9	6892	0	0	0
T10	8207	0	0	0
T11	44747	0	0	0
T12	5995	0	0	0
T13	90012	0	0	0
T24	0	7	0	0
T25	0	8	0	0
T26	0	6	0	0
T38	0	8	0	0
T43	0	8	0	0
T53	0	1	0	0
T77	0	3	0	0
T79	0	25	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	23288	0	0
T1	730	2	0	0
T2	432	6	0	0
T3	730	3	0	0
T4	20114	415	0	0
T5	632	17	0	0
T6	637	14	0	0
T7	459	13	0	0
T8	293	5	0	0
T9	430	5	0	0
T10	512	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	1077	0	0
T4	20114	6	0	0
T5	632	0	0	0
T6	637	0	0	0
T7	459	12	0	0
T8	293	0	0	0
T9	430	0	0	0
T10	512	0	0	0
T11	2882	0	0	0
T12	373	0	0	0
T13	5640	0	0	0
T24	0	9	0	0
T25	0	8	0	0
T26	0	5	0	0
T38	0	7	0	0
T43	0	8	0	0
T77	0	6	0	0
T79	0	27	0	0
T80	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	23288	0	0
T1	730	2	0	0
T2	432	6	0	0
T3	730	3	0	0
T4	20114	415	0	0
T5	632	17	0	0
T6	637	14	0	0
T7	459	13	0	0
T8	293	5	0	0
T9	430	5	0	0
T10	512	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1774719	1077	0	0
T4	20114	6	0	0
T5	632	0	0	0
T6	637	0	0	0
T7	459	12	0	0
T8	293	0	0	0
T9	430	0	0	0
T10	512	0	0	0
T11	2882	0	0	0
T12	373	0	0	0
T13	5640	0	0	0
T24	0	9	0	0
T25	0	8	0	0
T26	0	5	0	0
T38	0	7	0	0
T43	0	8	0	0
T77	0	6	0	0
T79	0	27	0	0
T80	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15434	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	14	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	4	0	0
T13	0	75	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1146	0	0
T4	156591	7	0	0
T5	5061	0	0	0
T6	5107	0	0	0
T7	3680	14	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	0	0	0
T13	45010	0	0	0
T24	0	9	0	0
T25	0	11	0	0
T26	0	7	0	0
T38	0	10	0	0
T43	0	7	0	0
T53	0	1	0	0
T77	0	8	0	0
T79	0	24	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15434	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	14	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	4	0	0
T13	0	75	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1146	0	0
T4	156591	7	0	0
T5	5061	0	0	0
T6	5107	0	0	0
T7	3680	14	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	0	0	0
T13	45010	0	0	0
T24	0	9	0	0
T25	0	11	0	0
T26	0	7	0	0
T38	0	10	0	0
T43	0	7	0	0
T53	0	1	0	0
T77	0	8	0	0
T79	0	24	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15471	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	14	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	4	0	0
T13	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1186	0	0
T4	156591	7	0	0
T5	5061	0	0	0
T6	5107	0	0	0
T7	3680	14	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	0	0	0
T13	45010	0	0	0
T24	0	11	0	0
T25	0	12	0	0
T26	0	7	0	0
T38	0	9	0	0
T43	0	5	0	0
T77	0	9	0	0
T79	0	28	0	0
T80	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15471	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	14	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	4	0	0
T13	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1186	0	0
T4	156591	7	0	0
T5	5061	0	0	0
T6	5107	0	0	0
T7	3680	14	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	0	0	0
T13	45010	0	0	0
T24	0	11	0	0
T25	0	12	0	0
T26	0	7	0	0
T38	0	9	0	0
T43	0	5	0	0
T77	0	9	0	0
T79	0	28	0	0
T80	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15537	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	14	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	4	0	0
T13	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1240	0	0
T4	156591	8	0	0
T5	5061	0	0	0
T6	5107	0	0	0
T7	3680	14	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	0	0	0
T13	45010	0	0	0
T24	0	12	0	0
T25	0	13	0	0
T26	0	10	0	0
T38	0	11	0	0
T43	0	8	0	0
T77	0	9	0	0
T79	0	22	0	0
T81	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	15537	0	0
T2	3466	4	0	0
T3	5833	0	0	0
T4	156591	296	0	0
T5	5061	16	0	0
T6	5107	13	0	0
T7	3680	14	0	0
T8	2355	4	0	0
T9	3444	4	0	0
T10	4102	0	0	0
T11	22368	44	0	0
T12	0	4	0	0
T13	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14048957	1240	0	0
T4	156591	8	0	0
T5	5061	0	0	0
T6	5107	0	0	0
T7	3680	14	0	0
T8	2355	0	0	0
T9	3444	0	0	0
T10	4102	0	0	0
T11	22368	0	0	0
T12	2997	0	0	0
T13	45010	0	0	0
T24	0	12	0	0
T25	0	13	0	0
T26	0	10	0	0
T38	0	11	0	0
T43	0	8	0	0
T77	0	9	0	0
T79	0	22	0	0
T81	0	1	0	0