Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13213187	9866	0	0
alert_regwen_rd_A	13213187	6409	0	0
cpu_regwen_rd_A	13213187	6575	0	0
sw_rst_ctrl_n_0_rd_A	13213187	12548	0	0
sw_rst_ctrl_n_1_rd_A	13213187	12687	0	0
sw_rst_ctrl_n_2_rd_A	13213187	13070	0	0
sw_rst_ctrl_n_3_rd_A	13213187	12592	0	0
sw_rst_ctrl_n_4_rd_A	13213187	12386	0	0
sw_rst_ctrl_n_5_rd_A	13213187	12694	0	0
sw_rst_ctrl_n_6_rd_A	13213187	12748	0	0
sw_rst_ctrl_n_7_rd_A	13213187	12662	0	0
sw_rst_regwen_0_rd_A	13213187	6866	0	0
sw_rst_regwen_1_rd_A	13213187	7161	0	0
sw_rst_regwen_2_rd_A	13213187	7152	0	0
sw_rst_regwen_3_rd_A	13213187	6766	0	0
sw_rst_regwen_4_rd_A	13213187	7273	0	0
sw_rst_regwen_5_rd_A	13213187	7097	0	0
sw_rst_regwen_6_rd_A	13213187	7133	0	0
sw_rst_regwen_7_rd_A	13213187	7013	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	9866	0	0
T56	4603	18	0	0
T57	4571	18	0	0
T58	3353	120	0	0
T59	10580	1	0	0
T60	21314	4	0	0
T61	2748	6	0	0
T83	16996	1	0	0
T84	4243	639	0	0
T85	15283	583	0	0
T86	10897	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	6409	0	0
T44	40846	57	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	80	0	0
T75	0	133	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	156	0	0
T90	18016	0	0	0
T93	0	40	0	0
T94	0	541	0	0
T116	0	61	0	0
T117	0	471	0	0
T118	0	35	0	0
T119	0	323	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	6575	0	0
T44	40846	54	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	59	0	0
T75	0	125	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	115	0	0
T90	18016	0	0	0
T93	0	42	0	0
T94	0	575	0	0
T116	0	68	0	0
T117	0	474	0	0
T118	0	21	0	0
T119	0	342	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12548	0	0
T6	4305	35	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	76	0	0
T70	0	75	0	0
T75	0	254	0	0
T79	0	316	0	0
T93	0	42	0	0
T94	0	576	0	0
T121	0	85	0	0
T123	0	23	0	0
T124	0	179	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12687	0	0
T6	4305	42	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	49	0	0
T70	0	67	0	0
T75	0	268	0	0
T79	0	362	0	0
T93	0	50	0	0
T94	0	623	0	0
T121	0	73	0	0
T123	0	34	0	0
T124	0	205	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	13070	0	0
T6	4305	42	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	72	0	0
T70	0	65	0	0
T75	0	216	0	0
T79	0	381	0	0
T93	0	45	0	0
T94	0	682	0	0
T121	0	48	0	0
T123	0	17	0	0
T124	0	165	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12592	0	0
T6	4305	47	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	70	0	0
T70	0	64	0	0
T75	0	242	0	0
T79	0	349	0	0
T93	0	45	0	0
T94	0	589	0	0
T121	0	74	0	0
T123	0	27	0	0
T124	0	201	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12386	0	0
T6	4305	49	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	68	0	0
T70	0	81	0	0
T75	0	248	0	0
T79	0	373	0	0
T93	0	33	0	0
T94	0	561	0	0
T121	0	47	0	0
T123	0	30	0	0
T124	0	189	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12694	0	0
T6	4305	29	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	76	0	0
T70	0	70	0	0
T75	0	285	0	0
T79	0	348	0	0
T93	0	39	0	0
T94	0	631	0	0
T121	0	74	0	0
T123	0	21	0	0
T124	0	204	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12748	0	0
T6	4305	56	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	72	0	0
T70	0	92	0	0
T75	0	271	0	0
T79	0	378	0	0
T93	0	43	0	0
T94	0	544	0	0
T121	0	75	0	0
T123	0	29	0	0
T124	0	177	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	12662	0	0
T6	4305	52	0	0
T7	3662	0	0	0
T8	2115	0	0	0
T9	3300	0	0	0
T10	4012	0	0	0
T11	17588	0	0	0
T12	2612	0	0	0
T13	41926	0	0	0
T23	26072	0	0	0
T24	8116	0	0	0
T44	0	51	0	0
T70	0	78	0	0
T75	0	247	0	0
T79	0	442	0	0
T93	0	48	0	0
T94	0	561	0	0
T121	0	70	0	0
T123	0	25	0	0
T124	0	186	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	6866	0	0
T44	40846	86	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	77	0	0
T75	0	123	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	151	0	0
T90	18016	0	0	0
T93	0	35	0	0
T94	0	600	0	0
T116	0	46	0	0
T117	0	395	0	0
T118	0	17	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	35	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	7161	0	0
T44	40846	70	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	56	0	0
T75	0	111	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	187	0	0
T90	18016	0	0	0
T93	0	44	0	0
T94	0	606	0	0
T116	0	60	0	0
T117	0	466	0	0
T118	0	28	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	16	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	7152	0	0
T44	40846	81	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	71	0	0
T75	0	152	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	179	0	0
T90	18016	0	0	0
T93	0	40	0	0
T94	0	573	0	0
T116	0	38	0	0
T117	0	435	0	0
T118	0	28	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	18	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	6766	0	0
T44	40846	89	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	67	0	0
T75	0	105	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	114	0	0
T90	18016	0	0	0
T93	0	49	0	0
T94	0	511	0	0
T116	0	55	0	0
T117	0	433	0	0
T118	0	25	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	31	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	7273	0	0
T44	40846	69	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	58	0	0
T75	0	135	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	141	0	0
T90	18016	0	0	0
T93	0	28	0	0
T94	0	528	0	0
T116	0	46	0	0
T117	0	506	0	0
T118	0	34	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	32	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	7097	0	0
T44	40846	109	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	43	0	0
T75	0	133	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	123	0	0
T90	18016	0	0	0
T93	0	46	0	0
T94	0	560	0	0
T116	0	52	0	0
T117	0	441	0	0
T118	0	24	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	35	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	7133	0	0
T44	40846	67	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	61	0	0
T75	0	126	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	118	0	0
T90	18016	0	0	0
T93	0	61	0	0
T94	0	523	0	0
T116	0	62	0	0
T117	0	437	0	0
T118	0	13	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	17	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13213187	7013	0	0
T44	40846	63	0	0
T45	19452	0	0	0
T54	5097	0	0	0
T65	1835	0	0	0
T70	0	72	0	0
T75	0	138	0	0
T76	2287	0	0	0
T77	6894	0	0	0
T79	0	153	0	0
T90	18016	0	0	0
T93	0	41	0	0
T94	0	556	0	0
T116	0	43	0	0
T117	0	459	0	0
T118	0	17	0	0
T120	5125	0	0	0
T121	5627	0	0	0
T122	2293	0	0	0
T124	0	14	0	0