RSTMGR Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.620s	262.999us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.930s	99.487us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.890s	59.230us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	10.940s	2.304ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.660s	433.203us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.810s	188.657us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.890s	59.230us	20	20	100.00
		rstmgr_csr_aliasing	2.660s	433.203us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.060s	219.315us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.980s	534.860us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.590s	287.234us	50	50	100.00
V2	reset_info	rstmgr_reset	8.150s	2.086ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.150s	2.086ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.150s	2.086ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.150s	2.086ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	1.006m	17.322ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.880s	129.994us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.990s	639.832us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.990s	639.832us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.930s	99.487us	5	5	100.00
		rstmgr_csr_rw	0.890s	59.230us	20	20	100.00
		rstmgr_csr_aliasing	2.660s	433.203us	5	5	100.00
		rstmgr_same_csr_outstanding	1.660s	225.694us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.930s	99.487us	5	5	100.00
		rstmgr_csr_rw	0.890s	59.230us	20	20	100.00
		rstmgr_csr_aliasing	2.660s	433.203us	5	5	100.00
		rstmgr_same_csr_outstanding	1.660s	225.694us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	30.350s	16.525ms	5	5	100.00
		rstmgr_tl_intg_err	3.290s	934.964us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	30.350s	16.525ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	30.350s	16.525ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.290s	934.964us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.300s	176.285us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.080s	2.374ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.180s	244.450us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	30.350s	16.525ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.890s	59.230us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.890s	59.230us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.88	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.04.26_08.15.50
• 2024.04.24_08.22.42
• 2024.04.22_07.52.26
• 2024.04.19_05.31.42
• 2024.04.17_05.39.22