Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	602536	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363147

1

T2

78

T3

65

T4

393

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515299	1			T2	99		T3	99		T4	547
values[0x0]	225102	1			T2	56		T3	58		T4	241
values[0x1]	225282	1			T2	57		T3	55		T4	260

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	505095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460588

1

T2

103

T3

92

T4

491

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3415	1			T5	12		T7	1		T8	1
valid_sources[0x01]	4271	1			T2	1		T5	26		T7	1
valid_sources[0x02]	4219	1			T5	19		T8	1		T10	4
valid_sources[0x03]	2943	1			T2	1		T5	46		T7	1
valid_sources[0x04]	3462	1			T2	1		T5	31		T8	9
valid_sources[0x05]	3376	1			T5	27		T7	1		T10	3
valid_sources[0x06]	2558	1			T3	2		T5	31		T7	1
valid_sources[0x07]	3190	1			T2	1		T5	18		T7	1
valid_sources[0x08]	3211	1			T2	3		T5	12		T7	1
valid_sources[0x09]	3002	1			T2	1		T5	14		T7	2
valid_sources[0x0a]	3648	1			T3	13		T5	10		T8	3
valid_sources[0x0b]	6031	1			T3	4		T5	5		T7	1
valid_sources[0x0c]	2826	1			T3	9		T5	39		T7	1
valid_sources[0x0d]	3057	1			T2	1		T5	29		T8	18
valid_sources[0x0e]	4109	1			T5	15		T8	7		T10	2
valid_sources[0x0f]	3283	1			T2	1		T5	12		T7	1
valid_sources[0x10]	3148	1			T2	4		T5	10		T10	5
valid_sources[0x11]	6192	1			T5	43		T8	10		T10	4
valid_sources[0x12]	3165	1			T5	22		T8	10		T10	4
valid_sources[0x13]	3249	1			T2	2		T3	1		T5	29
valid_sources[0x14]	3084	1			T2	2		T5	48		T6	1
valid_sources[0x15]	3182	1			T2	1		T5	19		T8	9
valid_sources[0x16]	4117	1			T2	1		T5	36		T7	1
valid_sources[0x17]	3405	1			T3	1		T5	28		T10	2
valid_sources[0x18]	2934	1			T5	23		T7	1		T10	4
valid_sources[0x19]	3136	1			T2	1		T5	28		T8	4
valid_sources[0x1a]	2816	1			T3	1		T5	28		T8	3
valid_sources[0x1b]	3585	1			T2	1		T5	45		T8	3
valid_sources[0x1c]	2788	1			T5	16		T8	3		T10	2
valid_sources[0x1d]	3275	1			T2	1		T5	47		T8	3
valid_sources[0x1e]	3366	1			T5	37		T8	4		T10	3
valid_sources[0x1f]	4098	1			T2	1		T5	42		T10	3
valid_sources[0x20]	3328	1			T5	20		T8	7		T10	6
valid_sources[0x21]	4710	1			T2	1		T3	2		T5	53
valid_sources[0x22]	3349	1			T2	4		T3	16		T5	46
valid_sources[0x23]	3049	1			T2	2		T3	11		T5	8
valid_sources[0x24]	4169	1			T5	20		T6	1		T10	4
valid_sources[0x25]	3634	1			T5	19		T6	1		T8	3
valid_sources[0x26]	3323	1			T2	1		T5	9		T7	1
valid_sources[0x27]	3147	1			T5	15		T8	4		T10	7
valid_sources[0x28]	3582	1			T2	1		T3	2		T5	32
valid_sources[0x29]	3877	1			T5	26		T6	1		T7	2
valid_sources[0x2a]	3729	1			T3	9		T5	25		T7	1
valid_sources[0x2b]	3322	1			T2	1		T5	33		T7	1
valid_sources[0x2c]	2825	1			T3	11		T5	53		T7	1
valid_sources[0x2d]	4794	1			T2	3		T5	14		T10	1
valid_sources[0x2e]	2860	1			T2	1		T5	38		T8	2
valid_sources[0x2f]	3155	1			T2	1		T5	26		T7	1
valid_sources[0x30]	2572	1			T5	13		T8	7		T10	2
valid_sources[0x31]	3560	1			T5	38		T7	2		T8	10
valid_sources[0x32]	3429	1			T5	24		T7	1		T8	6
valid_sources[0x33]	7071	1			T5	30		T8	11		T10	5
valid_sources[0x34]	3242	1			T2	3		T3	2		T5	14
valid_sources[0x35]	3564	1			T2	1		T5	6		T7	2
valid_sources[0x36]	3713	1			T5	34		T10	2		T11	11
valid_sources[0x37]	4459	1			T2	1		T3	1		T5	44
valid_sources[0x38]	4253	1			T5	37		T8	4		T10	1
valid_sources[0x39]	6177	1			T2	1		T3	1		T5	13
valid_sources[0x3a]	3725	1			T5	35		T10	2		T11	8
valid_sources[0x3b]	3883	1			T5	73		T8	1		T10	6
valid_sources[0x3c]	3554	1			T2	1		T5	26		T7	2
valid_sources[0x3d]	5023	1			T5	38		T8	2		T10	5
valid_sources[0x3e]	3776	1			T2	2		T5	25		T7	1
valid_sources[0x3f]	3291	1			T2	1		T3	3		T5	48
valid_sources[0x40]	3177	1			T5	45		T7	2		T8	12
valid_sources[0x41]	4433	1			T2	1		T4	1048		T5	42
valid_sources[0x42]	3203	1			T5	29		T8	4		T10	4
valid_sources[0x43]	2869	1			T5	14		T8	4		T10	1
valid_sources[0x44]	2884	1			T2	1		T5	35		T10	2
valid_sources[0x45]	3440	1			T2	1		T5	67		T7	1
valid_sources[0x46]	3225	1			T2	1		T5	27		T8	4
valid_sources[0x47]	3348	1			T2	1		T5	23		T8	1
valid_sources[0x48]	3627	1			T2	1		T5	27		T7	1
valid_sources[0x49]	3742	1			T2	2		T5	29		T7	1
valid_sources[0x4a]	3083	1			T2	1		T5	10		T7	1
valid_sources[0x4b]	3316	1			T2	1		T5	8		T7	1
valid_sources[0x4c]	6658	1			T2	1		T5	28		T7	1
valid_sources[0x4d]	3659	1			T2	1		T5	19		T8	6
valid_sources[0x4e]	3057	1			T2	1		T5	24		T8	1
valid_sources[0x4f]	3439	1			T3	2		T5	20		T10	5
valid_sources[0x50]	3499	1			T2	2		T5	30		T8	7
valid_sources[0x51]	3402	1			T2	1		T5	22		T6	1
valid_sources[0x52]	4543	1			T5	20		T10	4		T11	18
valid_sources[0x53]	3724	1			T2	2		T5	33		T8	9
valid_sources[0x54]	3759	1			T5	42		T8	2		T10	8
valid_sources[0x55]	3601	1			T2	2		T5	13		T8	4
valid_sources[0x56]	2933	1			T2	1		T5	13		T7	2
valid_sources[0x57]	3665	1			T5	18		T8	2		T10	9
valid_sources[0x58]	4025	1			T5	2		T8	7		T10	6
valid_sources[0x59]	3202	1			T2	2		T5	14		T8	4
valid_sources[0x5a]	3111	1			T5	11		T8	3		T10	2
valid_sources[0x5b]	4015	1			T2	1		T5	46		T8	7
valid_sources[0x5c]	3035	1			T5	60		T7	1		T8	5
valid_sources[0x5d]	3132	1			T5	37		T8	3		T10	2
valid_sources[0x5e]	4286	1			T2	1		T3	11		T5	16
valid_sources[0x5f]	6092	1			T3	7		T5	31		T10	4
valid_sources[0x60]	3503	1			T5	42		T10	2		T11	15
valid_sources[0x61]	3389	1			T2	5		T5	20		T8	4
valid_sources[0x62]	4364	1			T5	57		T8	5		T10	1
valid_sources[0x63]	3971	1			T5	39		T8	3		T10	3
valid_sources[0x64]	2738	1			T2	4		T5	28		T7	1
valid_sources[0x65]	3458	1			T2	1		T5	50		T8	1
valid_sources[0x66]	3346	1			T2	1		T5	13		T8	2
valid_sources[0x67]	3359	1			T3	4		T5	44		T7	3
valid_sources[0x68]	3070	1			T2	1		T5	34		T8	8
valid_sources[0x69]	4168	1			T2	1		T5	15		T7	2
valid_sources[0x6a]	3167	1			T2	1		T3	1		T5	33
valid_sources[0x6b]	2985	1			T2	1		T5	20		T7	1
valid_sources[0x6c]	6391	1			T2	1		T5	38		T6	1
valid_sources[0x6d]	2725	1			T5	6		T7	2		T8	3
valid_sources[0x6e]	3386	1			T2	3		T5	14		T7	1
valid_sources[0x6f]	3168	1			T2	2		T5	15		T6	1
valid_sources[0x70]	3050	1			T2	1		T5	59		T8	1
valid_sources[0x71]	3182	1			T2	2		T5	21		T6	1
valid_sources[0x72]	3251	1			T2	1		T5	18		T7	2
valid_sources[0x73]	4251	1			T2	2		T5	51		T7	1
valid_sources[0x74]	3450	1			T5	36		T10	6		T11	9
valid_sources[0x75]	3411	1			T2	3		T5	53		T8	3
valid_sources[0x76]	3920	1			T2	1		T5	35		T7	2
valid_sources[0x77]	3204	1			T3	21		T5	25		T7	1
valid_sources[0x78]	4062	1			T5	43		T7	1		T8	12
valid_sources[0x79]	3663	1			T2	1		T5	20		T8	2
valid_sources[0x7a]	3153	1			T2	2		T5	4		T8	10
valid_sources[0x7b]	2662	1			T2	1		T5	32		T6	1
valid_sources[0x7c]	3380	1			T2	1		T5	7		T6	1
valid_sources[0x7d]	6007	1			T2	1		T3	6		T5	50
valid_sources[0x7e]	2606	1			T5	13		T8	1		T10	4
valid_sources[0x7f]	3205	1			T2	3		T5	21		T8	1
valid_sources[0x80]	3155	1			T5	26		T8	3		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

242204

1

T2

43

T3

39

T4

264

values[0x0]

all_enables

biggest_size

78792

1

T2

22

T3

21

T4

83

values[0x1]

all_enables

biggest_size

42151

1

T2

13

T3

5

T4

46