Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11393722	12854	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11393722	118511	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11393722	6824667	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11393722	189243	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11393722	12854	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11393722	118511	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11393722	6824667	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11393722	189243	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	12854	0	0
T2	3197	4	0	0
T3	3903	4	0	0
T4	3603	0	0	0
T5	103195	85	0	0
T6	1789	0	0	0
T7	1860	7	0	0
T8	3358	0	0	0
T9	1475	1	0	0
T10	10748	0	0	0
T11	53428	75	0	0
T12	0	30	0	0
T13	0	145	0	0
T14	0	3	0	0
T15	0	75	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	118511	0	0
T2	3197	38	0	0
T3	3903	37	0	0
T4	3603	0	0	0
T5	103195	769	0	0
T6	1789	0	0	0
T7	1860	63	0	0
T8	3358	0	0	0
T9	1475	9	0	0
T10	10748	0	0	0
T11	53428	700	0	0
T12	0	271	0	0
T13	0	1334	0	0
T14	0	27	0	0
T15	0	700	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	6824667	0	0
T1	5664	562	0	0
T2	3197	2190	0	0
T3	3903	2964	0	0
T4	3603	2982	0	0
T5	103195	82924	0	0
T6	1789	1192	0	0
T7	1860	1184	0	0
T8	3358	2757	0	0
T9	1475	862	0	0
T10	10748	10103	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	189243	0	0
T2	3197	58	0	0
T3	3903	62	0	0
T4	3603	0	0	0
T5	103195	1277	0	0
T6	1789	0	0	0
T7	1860	98	0	0
T8	3358	0	0	0
T9	1475	13	0	0
T10	10748	0	0	0
T11	53428	1050	0	0
T12	0	468	0	0
T13	0	2201	0	0
T14	0	35	0	0
T15	0	1078	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	12854	0	0
T2	3197	4	0	0
T3	3903	4	0	0
T4	3603	0	0	0
T5	103195	85	0	0
T6	1789	0	0	0
T7	1860	7	0	0
T8	3358	0	0	0
T9	1475	1	0	0
T10	10748	0	0	0
T11	53428	75	0	0
T12	0	30	0	0
T13	0	145	0	0
T14	0	3	0	0
T15	0	75	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	118511	0	0
T2	3197	38	0	0
T3	3903	37	0	0
T4	3603	0	0	0
T5	103195	769	0	0
T6	1789	0	0	0
T7	1860	63	0	0
T8	3358	0	0	0
T9	1475	9	0	0
T10	10748	0	0	0
T11	53428	700	0	0
T12	0	271	0	0
T13	0	1334	0	0
T14	0	27	0	0
T15	0	700	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	6824667	0	0
T1	5664	562	0	0
T2	3197	2190	0	0
T3	3903	2964	0	0
T4	3603	2982	0	0
T5	103195	82924	0	0
T6	1789	1192	0	0
T7	1860	1184	0	0
T8	3358	2757	0	0
T9	1475	862	0	0
T10	10748	10103	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	189243	0	0
T2	3197	58	0	0
T3	3903	62	0	0
T4	3603	0	0	0
T5	103195	1277	0	0
T6	1789	0	0	0
T7	1860	98	0	0
T8	3358	0	0	0
T9	1475	13	0	0
T10	10748	0	0	0
T11	53428	1050	0	0
T12	0	468	0	0
T13	0	2201	0	0
T14	0	35	0	0
T15	0	1078	0	0