Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T3,T5,T12
1	0	Covered	T5,T12,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53680412	8539	0	0
CascadeEffAonToRstPorAboveRise_A	53680412	8539	0	0
CascadeEffAonToRstPorIoAboveFall_A	51531302	8539	0	0
CascadeEffAonToRstPorIoAboveRise_A	51531302	8539	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25766709	8539	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25766709	8539	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12882967	8539	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12882967	8539	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25766780	8539	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25766780	8539	0	0
CascadeLcToLcAboveFall_A	53680412	21393	0	0
CascadeLcToLcAboveRise_A	53680412	21393	0	0
CascadeLcToLcAonAboveFall_A	1626077	21393	0	0
CascadeLcToLcAonAboveRise_A	1626077	21393	0	0
CascadeLcToLcShadowedAboveFall_A	53680412	21393	0	0
CascadeLcToLcShadowedAboveRise_A	53680412	21393	0	0
CascadePorToAonAboveFall_A	1626077	6732	0	0
CascadeSysToSysAboveFall_A	53680412	21393	0	0
CascadeSysToSysAboveRise_A	53680412	21393	0	0
ScanRstToAonRise_A	1626077	220	0	0
StablePorToAonRise_A	1626077	8539	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11393722	21393	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11393722	21393	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11393722	21393	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11393722	21393	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12882967	21393	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12882967	21393	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11393722	21393	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11393722	21393	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11393722	21393	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11393722	21393	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	8539	0	0
T1	24282	8	0	0
T2	13734	2	0	0
T3	17666	2	0	0
T4	15194	1	0	0
T5	478154	42	0	0
T6	7740	1	0	0
T7	9851	1	0	0
T8	14272	1	0	0
T9	6856	1	0	0
T10	44864	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	8539	0	0
T1	24282	8	0	0
T2	13734	2	0	0
T3	17666	2	0	0
T4	15194	1	0	0
T5	478154	42	0	0
T6	7740	1	0	0
T7	9851	1	0	0
T8	14272	1	0	0
T9	6856	1	0	0
T10	44864	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51531302	8539	0	0
T1	23300	8	0	0
T2	13180	2	0	0
T3	16963	2	0	0
T4	14586	1	0	0
T5	459048	42	0	0
T6	7430	1	0	0
T7	9457	1	0	0
T8	13701	1	0	0
T9	6581	1	0	0
T10	43068	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51531302	8539	0	0
T1	23300	8	0	0
T2	13180	2	0	0
T3	16963	2	0	0
T4	14586	1	0	0
T5	459048	42	0	0
T6	7430	1	0	0
T7	9457	1	0	0
T8	13701	1	0	0
T9	6581	1	0	0
T10	43068	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766709	8539	0	0
T1	11646	8	0	0
T2	6592	2	0	0
T3	8479	2	0	0
T4	7293	1	0	0
T5	229533	42	0	0
T6	3713	1	0	0
T7	4728	1	0	0
T8	6849	1	0	0
T9	3290	1	0	0
T10	21534	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766709	8539	0	0
T1	11646	8	0	0
T2	6592	2	0	0
T3	8479	2	0	0
T4	7293	1	0	0
T5	229533	42	0	0
T6	3713	1	0	0
T7	4728	1	0	0
T8	6849	1	0	0
T9	3290	1	0	0
T10	21534	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	8539	0	0
T1	5825	8	0	0
T2	3294	2	0	0
T3	4241	2	0	0
T4	3645	1	0	0
T5	114756	42	0	0
T6	1856	1	0	0
T7	2364	1	0	0
T8	3424	1	0	0
T9	1644	1	0	0
T10	10767	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	8539	0	0
T1	5825	8	0	0
T2	3294	2	0	0
T3	4241	2	0	0
T4	3645	1	0	0
T5	114756	42	0	0
T6	1856	1	0	0
T7	2364	1	0	0
T8	3424	1	0	0
T9	1644	1	0	0
T10	10767	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766780	8539	0	0
T1	11649	8	0	0
T2	6592	2	0	0
T3	8480	2	0	0
T4	7293	1	0	0
T5	229543	42	0	0
T6	3713	1	0	0
T7	4728	1	0	0
T8	6849	1	0	0
T9	3290	1	0	0
T10	21534	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766780	8539	0	0
T1	11649	8	0	0
T2	6592	2	0	0
T3	8480	2	0	0
T4	7293	1	0	0
T5	229543	42	0	0
T6	3713	1	0	0
T7	4728	1	0	0
T8	6849	1	0	0
T9	3290	1	0	0
T10	21534	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	21393	0	0
T1	24282	8	0	0
T2	13734	6	0	0
T3	17666	6	0	0
T4	15194	1	0	0
T5	478154	127	0	0
T6	7740	1	0	0
T7	9851	8	0	0
T8	14272	1	0	0
T9	6856	2	0	0
T10	44864	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	21393	0	0
T1	24282	8	0	0
T2	13734	6	0	0
T3	17666	6	0	0
T4	15194	1	0	0
T5	478154	127	0	0
T6	7740	1	0	0
T7	9851	8	0	0
T8	14272	1	0	0
T9	6856	2	0	0
T10	44864	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	21393	0	0
T1	729	8	0	0
T2	411	6	0	0
T3	529	6	0	0
T4	454	1	0	0
T5	14508	127	0	0
T6	231	1	0	0
T7	293	8	0	0
T8	426	1	0	0
T9	204	2	0	0
T10	1344	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	21393	0	0
T1	729	8	0	0
T2	411	6	0	0
T3	529	6	0	0
T4	454	1	0	0
T5	14508	127	0	0
T6	231	1	0	0
T7	293	8	0	0
T8	426	1	0	0
T9	204	2	0	0
T10	1344	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	21393	0	0
T1	24282	8	0	0
T2	13734	6	0	0
T3	17666	6	0	0
T4	15194	1	0	0
T5	478154	127	0	0
T6	7740	1	0	0
T7	9851	8	0	0
T8	14272	1	0	0
T9	6856	2	0	0
T10	44864	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	21393	0	0
T1	24282	8	0	0
T2	13734	6	0	0
T3	17666	6	0	0
T4	15194	1	0	0
T5	478154	127	0	0
T6	7740	1	0	0
T7	9851	8	0	0
T8	14272	1	0	0
T9	6856	2	0	0
T10	44864	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	6732	0	0
T1	729	8	0	0
T2	411	1	0	0
T3	529	1	0	0
T4	454	1	0	0
T5	14508	25	0	0
T6	231	1	0	0
T7	293	1	0	0
T8	426	1	0	0
T9	204	1	0	0
T10	1344	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	21393	0	0
T1	24282	8	0	0
T2	13734	6	0	0
T3	17666	6	0	0
T4	15194	1	0	0
T5	478154	127	0	0
T6	7740	1	0	0
T7	9851	8	0	0
T8	14272	1	0	0
T9	6856	2	0	0
T10	44864	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53680412	21393	0	0
T1	24282	8	0	0
T2	13734	6	0	0
T3	17666	6	0	0
T4	15194	1	0	0
T5	478154	127	0	0
T6	7740	1	0	0
T7	9851	8	0	0
T8	14272	1	0	0
T9	6856	2	0	0
T10	44864	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	220	0	0
T12	4764	1	0	0
T13	22054	2	0	0
T14	241	0	0	0
T15	3681	0	0	0
T16	735	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T44	504	0	0	0
T45	2259	1	0	0
T46	4064	0	0	0
T47	210	0	0	0
T64	2785	1	0	0
T91	0	1	0	0
T105	0	2	0	0
T106	0	2	0	0
T137	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	8539	0	0
T1	729	8	0	0
T2	411	2	0	0
T3	529	2	0	0
T4	454	1	0	0
T5	14508	42	0	0
T6	231	1	0	0
T7	293	1	0	0
T8	426	1	0	0
T9	204	1	0	0
T10	1344	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	21393	0	0
T1	5825	8	0	0
T2	3294	6	0	0
T3	4241	6	0	0
T4	3645	1	0	0
T5	114756	127	0	0
T6	1856	1	0	0
T7	2364	8	0	0
T8	3424	1	0	0
T9	1644	2	0	0
T10	10767	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	21393	0	0
T1	5825	8	0	0
T2	3294	6	0	0
T3	4241	6	0	0
T4	3645	1	0	0
T5	114756	127	0	0
T6	1856	1	0	0
T7	2364	8	0	0
T8	3424	1	0	0
T9	1644	2	0	0
T10	10767	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11393722	21393	0	0
T1	5664	8	0	0
T2	3197	6	0	0
T3	3903	6	0	0
T4	3603	1	0	0
T5	103195	127	0	0
T6	1789	1	0	0
T7	1860	8	0	0
T8	3358	1	0	0
T9	1475	2	0	0
T10	10748	1	0	0