Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12882967	13737	0	0
gen_assertions[0].RstEnOn_A	12882967	1054	0	0
gen_assertions[0].RstNOff_A	12882967	13737	0	0
gen_assertions[0].RstNOn_A	12882967	1054	0	0
gen_assertions[1].RstEnOff_A	51531302	12388	0	0
gen_assertions[1].RstEnOn_A	51531302	940	0	0
gen_assertions[1].RstNOff_A	51531302	12388	0	0
gen_assertions[1].RstNOn_A	51531302	940	0	0
gen_assertions[2].RstEnOff_A	25766709	12470	0	0
gen_assertions[2].RstEnOn_A	25766709	977	0	0
gen_assertions[2].RstNOff_A	25766709	12470	0	0
gen_assertions[2].RstNOn_A	25766709	977	0	0
gen_assertions[3].RstEnOff_A	25766780	12508	0	0
gen_assertions[3].RstEnOn_A	25766780	1005	0	0
gen_assertions[3].RstNOff_A	25766780	12508	0	0
gen_assertions[3].RstNOn_A	25766780	1005	0	0
gen_assertions[4].RstEnOff_A	1626077	21309	0	0
gen_assertions[4].RstEnOn_A	1626077	1075	0	0
gen_assertions[4].RstNOff_A	1626077	21309	0	0
gen_assertions[4].RstNOn_A	1626077	1075	0	0
gen_assertions[5].RstEnOff_A	12882967	13961	0	0
gen_assertions[5].RstEnOn_A	12882967	1135	0	0
gen_assertions[5].RstNOff_A	12882967	13961	0	0
gen_assertions[5].RstNOn_A	12882967	1135	0	0
gen_assertions[6].RstEnOff_A	12882967	14001	0	0
gen_assertions[6].RstEnOn_A	12882967	1178	0	0
gen_assertions[6].RstNOff_A	12882967	14001	0	0
gen_assertions[6].RstNOn_A	12882967	1178	0	0
gen_assertions[7].RstEnOff_A	12882967	14046	0	0
gen_assertions[7].RstEnOn_A	12882967	1221	0	0
gen_assertions[7].RstNOff_A	12882967	14046	0	0
gen_assertions[7].RstNOn_A	12882967	1221	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	13737	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	8	0	0
T5	114756	103	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	4	0	0
T9	1644	1	0	0
T10	10767	5	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1054	0	0
T4	3645	8	0	0
T5	114756	18	0	0
T6	1856	0	0	0
T7	2364	2	0	0
T8	3424	4	0	0
T9	1644	1	0	0
T10	10767	5	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T53	0	1	0	0
T65	0	5	0	0
T88	0	4	0	0
T89	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	13737	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	8	0	0
T5	114756	103	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	4	0	0
T9	1644	1	0	0
T10	10767	5	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1054	0	0
T4	3645	8	0	0
T5	114756	18	0	0
T6	1856	0	0	0
T7	2364	2	0	0
T8	3424	4	0	0
T9	1644	1	0	0
T10	10767	5	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T53	0	1	0	0
T65	0	5	0	0
T88	0	4	0	0
T89	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51531302	12388	0	0
T2	13180	4	0	0
T3	16963	4	0	0
T4	14586	9	0	0
T5	459048	91	0	0
T6	7430	0	0	0
T7	9457	6	0	0
T8	13701	5	0	0
T9	6581	1	0	0
T10	43068	6	0	0
T11	226859	69	0	0
T12	0	28	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51531302	940	0	0
T4	14586	9	0	0
T5	459048	14	0	0
T6	7430	0	0	0
T7	9457	2	0	0
T8	13701	5	0	0
T9	6581	0	0	0
T10	43068	6	0	0
T11	226859	0	0	0
T12	150499	0	0	0
T14	0	2	0	0
T16	23452	0	0	0
T65	0	8	0	0
T90	0	4	0	0
T91	0	1	0	0
T92	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51531302	12388	0	0
T2	13180	4	0	0
T3	16963	4	0	0
T4	14586	9	0	0
T5	459048	91	0	0
T6	7430	0	0	0
T7	9457	6	0	0
T8	13701	5	0	0
T9	6581	1	0	0
T10	43068	6	0	0
T11	226859	69	0	0
T12	0	28	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51531302	940	0	0
T4	14586	9	0	0
T5	459048	14	0	0
T6	7430	0	0	0
T7	9457	2	0	0
T8	13701	5	0	0
T9	6581	0	0	0
T10	43068	6	0	0
T11	226859	0	0	0
T12	150499	0	0	0
T14	0	2	0	0
T16	23452	0	0	0
T65	0	8	0	0
T90	0	4	0	0
T91	0	1	0	0
T92	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766709	12470	0	0
T2	6592	4	0	0
T3	8479	4	0	0
T4	7293	7	0	0
T5	229533	99	0	0
T6	3713	0	0	0
T7	4728	6	0	0
T8	6849	6	0	0
T9	3290	1	0	0
T10	21534	8	0	0
T11	113426	69	0	0
T12	0	28	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766709	977	0	0
T4	7293	7	0	0
T5	229533	22	0	0
T6	3713	0	0	0
T7	4728	0	0	0
T8	6849	6	0	0
T9	3290	0	0	0
T10	21534	8	0	0
T11	113426	0	0	0
T12	75246	0	0	0
T14	0	1	0	0
T16	11732	0	0	0
T65	0	8	0	0
T89	0	1	0	0
T90	0	3	0	0
T92	0	3	0	0
T93	0	2	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766709	12470	0	0
T2	6592	4	0	0
T3	8479	4	0	0
T4	7293	7	0	0
T5	229533	99	0	0
T6	3713	0	0	0
T7	4728	6	0	0
T8	6849	6	0	0
T9	3290	1	0	0
T10	21534	8	0	0
T11	113426	69	0	0
T12	0	28	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766709	977	0	0
T4	7293	7	0	0
T5	229533	22	0	0
T6	3713	0	0	0
T7	4728	0	0	0
T8	6849	6	0	0
T9	3290	0	0	0
T10	21534	8	0	0
T11	113426	0	0	0
T12	75246	0	0	0
T14	0	1	0	0
T16	11732	0	0	0
T65	0	8	0	0
T89	0	1	0	0
T90	0	3	0	0
T92	0	3	0	0
T93	0	2	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766780	12508	0	0
T2	6592	4	0	0
T3	8480	4	0	0
T4	7293	5	0	0
T5	229543	95	0	0
T6	3713	0	0	0
T7	4728	6	0	0
T8	6849	10	0	0
T9	3290	1	0	0
T10	21534	9	0	0
T11	113449	69	0	0
T12	0	28	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766780	1005	0	0
T4	7293	5	0	0
T5	229543	18	0	0
T6	3713	0	0	0
T7	4728	0	0	0
T8	6849	10	0	0
T9	3290	0	0	0
T10	21534	9	0	0
T11	113449	0	0	0
T12	75251	0	0	0
T16	11729	0	0	0
T65	0	9	0	0
T90	0	4	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	3	0	0
T94	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766780	12508	0	0
T2	6592	4	0	0
T3	8480	4	0	0
T4	7293	5	0	0
T5	229543	95	0	0
T6	3713	0	0	0
T7	4728	6	0	0
T8	6849	10	0	0
T9	3290	1	0	0
T10	21534	9	0	0
T11	113449	69	0	0
T12	0	28	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25766780	1005	0	0
T4	7293	5	0	0
T5	229543	18	0	0
T6	3713	0	0	0
T7	4728	0	0	0
T8	6849	10	0	0
T9	3290	0	0	0
T10	21534	9	0	0
T11	113449	0	0	0
T12	75251	0	0	0
T16	11729	0	0	0
T65	0	9	0	0
T90	0	4	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	3	0	0
T94	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	21309	0	0
T1	729	2	0	0
T2	411	6	0	0
T3	529	6	0	0
T4	454	9	0	0
T5	14508	143	0	0
T6	231	1	0	0
T7	293	8	0	0
T8	426	12	0	0
T9	204	2	0	0
T10	1344	12	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	1075	0	0
T4	454	8	0	0
T5	14508	17	0	0
T6	231	0	0	0
T7	293	0	0	0
T8	426	11	0	0
T9	204	0	0	0
T10	1344	11	0	0
T11	7103	0	0	0
T12	4764	0	0	0
T16	735	0	0	0
T34	0	11	0	0
T65	0	8	0	0
T90	0	6	0	0
T92	0	3	0	0
T93	0	5	0	0
T94	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	21309	0	0
T1	729	2	0	0
T2	411	6	0	0
T3	529	6	0	0
T4	454	9	0	0
T5	14508	143	0	0
T6	231	1	0	0
T7	293	8	0	0
T8	426	12	0	0
T9	204	2	0	0
T10	1344	12	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626077	1075	0	0
T4	454	8	0	0
T5	14508	17	0	0
T6	231	0	0	0
T7	293	0	0	0
T8	426	11	0	0
T9	204	0	0	0
T10	1344	11	0	0
T11	7103	0	0	0
T12	4764	0	0	0
T16	735	0	0	0
T34	0	11	0	0
T65	0	8	0	0
T90	0	6	0	0
T92	0	3	0	0
T93	0	5	0	0
T94	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	13961	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	11	0	0
T5	114756	103	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	9	0	0
T9	1644	1	0	0
T10	10767	10	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1135	0	0
T4	3645	11	0	0
T5	114756	18	0	0
T6	1856	0	0	0
T7	2364	0	0	0
T8	3424	9	0	0
T9	1644	0	0	0
T10	10767	10	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T34	0	8	0	0
T65	0	10	0	0
T90	0	6	0	0
T92	0	1	0	0
T93	0	6	0	0
T94	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	13961	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	11	0	0
T5	114756	103	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	9	0	0
T9	1644	1	0	0
T10	10767	10	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1135	0	0
T4	3645	11	0	0
T5	114756	18	0	0
T6	1856	0	0	0
T7	2364	0	0	0
T8	3424	9	0	0
T9	1644	0	0	0
T10	10767	10	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T34	0	8	0	0
T65	0	10	0	0
T90	0	6	0	0
T92	0	1	0	0
T93	0	6	0	0
T94	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	14001	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	13	0	0
T5	114756	104	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	10	0	0
T9	1644	1	0	0
T10	10767	11	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1178	0	0
T4	3645	13	0	0
T5	114756	19	0	0
T6	1856	0	0	0
T7	2364	0	0	0
T8	3424	10	0	0
T9	1644	0	0	0
T10	10767	11	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T65	0	12	0	0
T66	0	1	0	0
T90	0	7	0	0
T92	0	1	0	0
T93	0	7	0	0
T95	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	14001	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	13	0	0
T5	114756	104	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	10	0	0
T9	1644	1	0	0
T10	10767	11	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1178	0	0
T4	3645	13	0	0
T5	114756	19	0	0
T6	1856	0	0	0
T7	2364	0	0	0
T8	3424	10	0	0
T9	1644	0	0	0
T10	10767	11	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T65	0	12	0	0
T66	0	1	0	0
T90	0	7	0	0
T92	0	1	0	0
T93	0	7	0	0
T95	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	14046	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	14	0	0
T5	114756	105	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	13	0	0
T9	1644	1	0	0
T10	10767	13	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1221	0	0
T4	3645	14	0	0
T5	114756	20	0	0
T6	1856	0	0	0
T7	2364	0	0	0
T8	3424	13	0	0
T9	1644	0	0	0
T10	10767	13	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T65	0	12	0	0
T66	0	1	0	0
T89	0	1	0	0
T90	0	10	0	0
T92	0	1	0	0
T93	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	14046	0	0
T2	3294	4	0	0
T3	4241	4	0	0
T4	3645	14	0	0
T5	114756	105	0	0
T6	1856	0	0	0
T7	2364	7	0	0
T8	3424	13	0	0
T9	1644	1	0	0
T10	10767	13	0	0
T11	56721	75	0	0
T12	0	30	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882967	1221	0	0
T4	3645	14	0	0
T5	114756	20	0	0
T6	1856	0	0	0
T7	2364	0	0	0
T8	3424	13	0	0
T9	1644	0	0	0
T10	10767	13	0	0
T11	56721	0	0	0
T12	37631	0	0	0
T16	5864	0	0	0
T65	0	12	0	0
T66	0	1	0	0
T89	0	1	0	0
T90	0	10	0	0
T92	0	1	0	0
T93	0	8	0	0