Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12115284	8345	0	0
alert_regwen_rd_A	12115284	5102	0	0
cpu_regwen_rd_A	12115284	4919	0	0
sw_rst_ctrl_n_0_rd_A	12115284	10974	0	0
sw_rst_ctrl_n_1_rd_A	12115284	10788	0	0
sw_rst_ctrl_n_2_rd_A	12115284	10723	0	0
sw_rst_ctrl_n_3_rd_A	12115284	10890	0	0
sw_rst_ctrl_n_4_rd_A	12115284	10799	0	0
sw_rst_ctrl_n_5_rd_A	12115284	10852	0	0
sw_rst_ctrl_n_6_rd_A	12115284	10765	0	0
sw_rst_ctrl_n_7_rd_A	12115284	11030	0	0
sw_rst_regwen_0_rd_A	12115284	5529	0	0
sw_rst_regwen_1_rd_A	12115284	5538	0	0
sw_rst_regwen_2_rd_A	12115284	5644	0	0
sw_rst_regwen_3_rd_A	12115284	5564	0	0
sw_rst_regwen_4_rd_A	12115284	5326	0	0
sw_rst_regwen_5_rd_A	12115284	5531	0	0
sw_rst_regwen_6_rd_A	12115284	5364	0	0
sw_rst_regwen_7_rd_A	12115284	5619	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	8345	0	0
T68	20511	1	0	0
T70	16930	3	0	0
T71	12647	1	0	0
T72	4457	22	0	0
T73	2090	5	0	0
T74	4453	333	0	0
T97	9118	1	0	0
T98	2571	6	0	0
T99	4501	28	0	0
T100	2368	16	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5102	0	0
T5	103195	136	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	0	0	0
T11	53428	0	0	0
T12	33067	54	0	0
T13	153003	195	0	0
T16	5702	0	0	0
T46	0	16	0	0
T105	0	45	0	0
T108	0	46	0	0
T109	0	172	0	0
T133	0	358	0	0
T134	0	71	0	0
T135	0	200	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	4919	0	0
T5	103195	129	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	0	0	0
T11	53428	0	0	0
T12	33067	53	0	0
T13	153003	143	0	0
T16	5702	0	0	0
T46	0	27	0	0
T105	0	51	0	0
T108	0	59	0	0
T109	0	98	0	0
T133	0	303	0	0
T134	0	86	0	0
T135	0	227	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10974	0	0
T5	103195	387	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	112	0	0
T11	53428	0	0	0
T12	33067	46	0	0
T13	153003	160	0	0
T16	5702	0	0	0
T46	0	16	0	0
T65	0	181	0	0
T88	0	42	0	0
T94	0	104	0	0
T105	0	51	0	0
T136	0	4	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10788	0	0
T5	103195	338	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	81	0	0
T11	53428	0	0	0
T12	33067	62	0	0
T13	153003	137	0	0
T16	5702	0	0	0
T46	0	40	0	0
T65	0	184	0	0
T88	0	53	0	0
T94	0	85	0	0
T105	0	52	0	0
T136	0	18	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10723	0	0
T5	103195	434	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	117	0	0
T11	53428	0	0	0
T12	33067	59	0	0
T13	153003	138	0	0
T16	5702	0	0	0
T46	0	44	0	0
T65	0	178	0	0
T88	0	28	0	0
T94	0	78	0	0
T105	0	32	0	0
T136	0	19	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10890	0	0
T5	103195	407	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	93	0	0
T11	53428	0	0	0
T12	33067	30	0	0
T13	153003	140	0	0
T16	5702	0	0	0
T46	0	32	0	0
T65	0	151	0	0
T88	0	68	0	0
T94	0	89	0	0
T105	0	57	0	0
T136	0	12	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10799	0	0
T5	103195	387	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	163	0	0
T11	53428	0	0	0
T12	33067	47	0	0
T13	153003	174	0	0
T16	5702	0	0	0
T46	0	32	0	0
T65	0	184	0	0
T88	0	46	0	0
T94	0	142	0	0
T105	0	44	0	0
T136	0	13	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10852	0	0
T5	103195	302	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	136	0	0
T11	53428	0	0	0
T12	33067	66	0	0
T13	153003	152	0	0
T16	5702	0	0	0
T46	0	18	0	0
T65	0	178	0	0
T88	0	45	0	0
T94	0	95	0	0
T105	0	52	0	0
T136	0	7	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	10765	0	0
T5	103195	403	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	99	0	0
T11	53428	0	0	0
T12	33067	32	0	0
T13	153003	191	0	0
T16	5702	0	0	0
T46	0	17	0	0
T65	0	170	0	0
T88	0	43	0	0
T94	0	100	0	0
T105	0	44	0	0
T136	0	24	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	11030	0	0
T5	103195	410	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	130	0	0
T11	53428	0	0	0
T12	33067	53	0	0
T13	153003	150	0	0
T16	5702	0	0	0
T46	0	5	0	0
T65	0	193	0	0
T88	0	60	0	0
T94	0	63	0	0
T105	0	40	0	0
T136	0	8	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5529	0	0
T5	103195	126	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	15	0	0
T11	53428	0	0	0
T12	33067	48	0	0
T13	153003	138	0	0
T16	5702	0	0	0
T46	0	38	0	0
T65	0	29	0	0
T94	0	31	0	0
T105	0	48	0	0
T108	0	54	0	0
T109	0	185	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5538	0	0
T5	103195	158	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	22	0	0
T11	53428	0	0	0
T12	33067	45	0	0
T13	153003	129	0	0
T16	5702	0	0	0
T46	0	27	0	0
T65	0	26	0	0
T94	0	32	0	0
T105	0	56	0	0
T108	0	63	0	0
T109	0	138	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5644	0	0
T5	103195	119	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	30	0	0
T11	53428	0	0	0
T12	33067	46	0	0
T13	153003	145	0	0
T16	5702	0	0	0
T46	0	37	0	0
T65	0	23	0	0
T94	0	25	0	0
T105	0	42	0	0
T108	0	55	0	0
T109	0	174	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5564	0	0
T5	103195	112	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	22	0	0
T11	53428	0	0	0
T12	33067	43	0	0
T13	153003	143	0	0
T16	5702	0	0	0
T46	0	27	0	0
T65	0	16	0	0
T94	0	11	0	0
T105	0	71	0	0
T108	0	42	0	0
T109	0	154	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5326	0	0
T5	103195	113	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	31	0	0
T11	53428	0	0	0
T12	33067	41	0	0
T13	153003	128	0	0
T16	5702	0	0	0
T46	0	17	0	0
T65	0	20	0	0
T94	0	22	0	0
T105	0	34	0	0
T108	0	49	0	0
T109	0	132	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5531	0	0
T5	103195	109	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	30	0	0
T11	53428	0	0	0
T12	33067	48	0	0
T13	153003	152	0	0
T16	5702	0	0	0
T46	0	37	0	0
T65	0	43	0	0
T94	0	24	0	0
T105	0	57	0	0
T108	0	49	0	0
T109	0	143	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5364	0	0
T5	103195	114	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	15	0	0
T11	53428	0	0	0
T12	33067	60	0	0
T13	153003	151	0	0
T16	5702	0	0	0
T46	0	37	0	0
T65	0	29	0	0
T94	0	17	0	0
T105	0	51	0	0
T108	0	49	0	0
T109	0	145	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12115284	5619	0	0
T5	103195	109	0	0
T6	1789	0	0	0
T7	1860	0	0	0
T8	3358	0	0	0
T9	1475	0	0	0
T10	10748	39	0	0
T11	53428	0	0	0
T12	33067	55	0	0
T13	153003	159	0	0
T16	5702	0	0	0
T46	0	17	0	0
T65	0	40	0	0
T94	0	4	0	0
T105	0	56	0	0
T108	0	46	0	0
T109	0	167	0	0