Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	630105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

379375

1

T1

137

T2

18

T3

1017

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	537377	1			T1	186		T2	36		T3	1533
values[0x0]	235663	1			T1	106		T2	16		T3	615
values[0x1]	236440	1			T1	87		T2	23		T3	632

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	529011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

480469

1

T1

175

T2

28

T3

1314

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4312	1			T3	7		T13	51		T23	1
valid_sources[0x01]	3742	1			T2	1		T3	10		T4	1
valid_sources[0x02]	3482	1			T3	7		T13	38		T25	15
valid_sources[0x03]	4047	1			T3	14		T4	1		T6	1
valid_sources[0x04]	3255	1			T3	15		T4	5		T6	1
valid_sources[0x05]	4726	1			T2	1		T3	8		T4	4
valid_sources[0x06]	3911	1			T3	15		T4	1		T13	40
valid_sources[0x07]	4409	1			T3	7		T13	63		T26	3
valid_sources[0x08]	6500	1			T2	1		T3	7		T12	2
valid_sources[0x09]	3671	1			T3	11		T4	3		T12	1
valid_sources[0x0a]	3449	1			T2	2		T3	13		T4	2
valid_sources[0x0b]	3856	1			T3	5		T4	1		T12	1
valid_sources[0x0c]	4275	1			T3	12		T4	2		T12	1
valid_sources[0x0d]	4060	1			T3	10		T4	1		T9	5
valid_sources[0x0e]	4062	1			T3	10		T12	1		T13	43
valid_sources[0x0f]	3417	1			T2	1		T3	12		T13	46
valid_sources[0x10]	3098	1			T3	8		T12	2		T13	48
valid_sources[0x11]	3290	1			T2	1		T3	8		T4	5
valid_sources[0x12]	3976	1			T3	15		T12	5		T13	35
valid_sources[0x13]	3513	1			T3	13		T4	3		T12	4
valid_sources[0x14]	4060	1			T3	10		T4	2		T9	4
valid_sources[0x15]	2979	1			T3	15		T13	47		T23	1
valid_sources[0x16]	3884	1			T3	15		T12	3		T13	54
valid_sources[0x17]	5064	1			T2	4		T3	9		T9	13
valid_sources[0x18]	3954	1			T3	8		T4	10		T6	1
valid_sources[0x19]	4650	1			T3	10		T9	9		T12	2
valid_sources[0x1a]	4556	1			T2	1		T3	10		T4	1
valid_sources[0x1b]	3712	1			T2	1		T3	10		T12	2
valid_sources[0x1c]	3214	1			T3	13		T4	3		T12	2
valid_sources[0x1d]	4058	1			T3	8		T4	1		T9	1
valid_sources[0x1e]	3228	1			T3	8		T12	4		T13	60
valid_sources[0x1f]	3392	1			T3	11		T12	1		T13	56
valid_sources[0x20]	4859	1			T3	14		T4	1		T9	8
valid_sources[0x21]	5336	1			T3	10		T4	2		T12	4
valid_sources[0x22]	4710	1			T3	11		T4	7		T12	1
valid_sources[0x23]	3246	1			T3	14		T4	12		T12	1
valid_sources[0x24]	3046	1			T3	9		T6	2		T12	2
valid_sources[0x25]	3627	1			T3	13		T4	2		T9	1
valid_sources[0x26]	4056	1			T3	16		T4	1		T12	2
valid_sources[0x27]	3934	1			T3	9		T4	2		T13	54
valid_sources[0x28]	6600	1			T3	10		T4	3		T9	8
valid_sources[0x29]	4881	1			T3	12		T6	14		T9	8
valid_sources[0x2a]	5180	1			T2	1		T3	9		T6	7
valid_sources[0x2b]	4947	1			T3	12		T9	23		T13	42
valid_sources[0x2c]	3589	1			T3	11		T4	1		T12	6
valid_sources[0x2d]	3615	1			T2	1		T3	5		T4	1
valid_sources[0x2e]	3175	1			T2	1		T3	5		T9	4
valid_sources[0x2f]	4980	1			T3	10		T4	1		T13	50
valid_sources[0x30]	3742	1			T3	9		T4	3		T12	1
valid_sources[0x31]	3292	1			T3	15		T12	2		T13	62
valid_sources[0x32]	3411	1			T3	11		T4	3		T12	1
valid_sources[0x33]	3537	1			T3	14		T12	5		T13	53
valid_sources[0x34]	4303	1			T3	7		T6	3		T13	53
valid_sources[0x35]	3470	1			T2	2		T3	11		T4	3
valid_sources[0x36]	3385	1			T3	18		T13	37		T24	1
valid_sources[0x37]	4043	1			T3	13		T4	2		T12	3
valid_sources[0x38]	4222	1			T3	10		T4	2		T12	2
valid_sources[0x39]	3716	1			T2	1		T3	19		T6	4
valid_sources[0x3a]	4180	1			T3	13		T12	2		T13	58
valid_sources[0x3b]	3335	1			T2	1		T3	10		T4	3
valid_sources[0x3c]	3181	1			T3	9		T9	6		T12	1
valid_sources[0x3d]	3247	1			T3	12		T4	1		T12	1
valid_sources[0x3e]	3677	1			T3	10		T4	6		T12	3
valid_sources[0x3f]	3245	1			T3	10		T4	1		T13	48
valid_sources[0x40]	5216	1			T3	14		T4	2		T12	2
valid_sources[0x41]	4050	1			T2	2		T3	10		T4	1
valid_sources[0x42]	3074	1			T3	11		T9	35		T12	3
valid_sources[0x43]	4483	1			T2	1		T3	8		T13	51
valid_sources[0x44]	3585	1			T3	9		T12	1		T13	45
valid_sources[0x45]	3153	1			T3	14		T4	1		T12	2
valid_sources[0x46]	3385	1			T3	14		T4	1		T9	28
valid_sources[0x47]	4356	1			T3	14		T12	2		T13	66
valid_sources[0x48]	3855	1			T3	11		T4	4		T9	3
valid_sources[0x49]	3650	1			T3	5		T4	3		T6	1
valid_sources[0x4a]	3709	1			T3	14		T4	2		T9	7
valid_sources[0x4b]	3844	1			T3	6		T6	2		T9	1
valid_sources[0x4c]	3585	1			T3	11		T9	15		T13	40
valid_sources[0x4d]	4030	1			T3	10		T4	3		T6	5
valid_sources[0x4e]	6740	1			T3	11		T8	3200		T9	9
valid_sources[0x4f]	3785	1			T3	11		T4	6		T12	3
valid_sources[0x50]	4356	1			T3	10		T4	2		T9	9
valid_sources[0x51]	3417	1			T3	11		T4	5		T12	2
valid_sources[0x52]	3862	1			T3	11		T4	3		T12	2
valid_sources[0x53]	3721	1			T3	17		T4	5		T9	36
valid_sources[0x54]	3125	1			T3	13		T9	6		T13	57
valid_sources[0x55]	3536	1			T3	3		T6	1		T12	1
valid_sources[0x56]	4925	1			T3	10		T12	1		T13	54
valid_sources[0x57]	4422	1			T3	9		T6	2		T13	49
valid_sources[0x58]	4874	1			T3	14		T4	3		T12	4
valid_sources[0x59]	4171	1			T3	12		T6	1		T13	42
valid_sources[0x5a]	3129	1			T3	7		T4	7		T13	51
valid_sources[0x5b]	3884	1			T3	15		T4	3		T12	1
valid_sources[0x5c]	4508	1			T3	11		T4	3		T9	17
valid_sources[0x5d]	3567	1			T3	14		T4	3		T12	4
valid_sources[0x5e]	4013	1			T2	1		T3	10		T4	3
valid_sources[0x5f]	3873	1			T3	10		T4	3		T13	46
valid_sources[0x60]	5069	1			T2	1		T3	10		T4	1
valid_sources[0x61]	3594	1			T3	10		T12	4		T13	26
valid_sources[0x62]	3668	1			T3	16		T13	81		T26	2
valid_sources[0x63]	3404	1			T2	1		T3	12		T4	2
valid_sources[0x64]	4378	1			T3	9		T4	1		T12	2
valid_sources[0x65]	3642	1			T3	11		T6	4		T13	54
valid_sources[0x66]	3600	1			T3	10		T4	2		T12	3
valid_sources[0x67]	3605	1			T2	1		T3	8		T4	1
valid_sources[0x68]	3534	1			T3	9		T4	1		T12	2
valid_sources[0x69]	3454	1			T3	12		T12	1		T13	42
valid_sources[0x6a]	3999	1			T3	12		T12	3		T13	46
valid_sources[0x6b]	3852	1			T2	1		T3	17		T13	39
valid_sources[0x6c]	3385	1			T2	2		T3	9		T4	2
valid_sources[0x6d]	2948	1			T3	13		T13	31		T24	2
valid_sources[0x6e]	3914	1			T3	9		T9	12		T12	4
valid_sources[0x6f]	6648	1			T3	6		T4	3		T12	1
valid_sources[0x70]	6461	1			T2	1		T3	8		T4	2
valid_sources[0x71]	3386	1			T3	14		T12	1		T13	30
valid_sources[0x72]	3161	1			T3	12		T4	6		T12	3
valid_sources[0x73]	3385	1			T2	1		T3	7		T4	1
valid_sources[0x74]	3690	1			T3	13		T6	1		T12	4
valid_sources[0x75]	3813	1			T3	9		T4	4		T13	45
valid_sources[0x76]	3469	1			T3	11		T13	37		T93	9
valid_sources[0x77]	2851	1			T3	13		T12	3		T13	28
valid_sources[0x78]	2883	1			T2	1		T3	11		T12	4
valid_sources[0x79]	3475	1			T3	12		T6	4		T12	1
valid_sources[0x7a]	4899	1			T3	14		T6	1		T12	1
valid_sources[0x7b]	3184	1			T3	10		T4	1		T13	45
valid_sources[0x7c]	4332	1			T3	13		T13	44		T24	1
valid_sources[0x7d]	4308	1			T3	11		T12	2		T13	89
valid_sources[0x7e]	3901	1			T3	12		T4	2		T12	4
valid_sources[0x7f]	5553	1			T3	6		T12	3		T13	54
valid_sources[0x80]	3561	1			T3	12		T4	2		T13	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

252188

1

T1

87

T2

15

T3

705

values[0x0]

all_enables

biggest_size

82770

1

T1

35

T2

1

T3

208

values[0x1]

all_enables

biggest_size

44417

1

T1

15

T2

2

T3

104