Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T13,T24
1	0	Covered	T1,T3,T4

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56364562	8986	0	0
CascadeEffAonToRstPorAboveRise_A	56364562	8986	0	0
CascadeEffAonToRstPorIoAboveFall_A	54108366	8986	0	0
CascadeEffAonToRstPorIoAboveRise_A	54108366	8986	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27054916	8986	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27054916	8986	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13527202	8986	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13527202	8986	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27055421	8986	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27055421	8986	0	0
CascadeLcToLcAboveFall_A	56364562	22404	0	0
CascadeLcToLcAboveRise_A	56364562	22404	0	0
CascadeLcToLcAonAboveFall_A	1708152	22404	0	0
CascadeLcToLcAonAboveRise_A	1708152	22404	0	0
CascadeLcToLcShadowedAboveFall_A	56364562	22404	0	0
CascadeLcToLcShadowedAboveRise_A	56364562	22404	0	0
CascadePorToAonAboveFall_A	1708152	7112	0	0
CascadeSysToSysAboveFall_A	56364562	22404	0	0
CascadeSysToSysAboveRise_A	56364562	22404	0	0
ScanRstToAonRise_A	1708152	205	0	0
StablePorToAonRise_A	1708152	8986	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12038585	22404	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12038585	22404	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12038585	22404	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12038585	22404	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13527202	22404	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13527202	22404	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12038585	22404	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12038585	22404	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12038585	22404	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12038585	22404	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	8986	0	0
T1	25169	2	0	0
T2	11589	1	0	0
T3	84432	17	0	0
T4	24533	2	0	0
T5	7437	1	0	0
T6	20270	3	0	0
T7	121862	27	0	0
T8	121894	27	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	8986	0	0
T1	25169	2	0	0
T2	11589	1	0	0
T3	84432	17	0	0
T4	24533	2	0	0
T5	7437	1	0	0
T6	20270	3	0	0
T7	121862	27	0	0
T8	121894	27	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54108366	8986	0	0
T1	24165	2	0	0
T2	11125	1	0	0
T3	81045	17	0	0
T4	23548	2	0	0
T5	7140	1	0	0
T6	19461	3	0	0
T7	116991	27	0	0
T8	117024	27	0	0
T9	46965	1	0	0
T10	23357	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54108366	8986	0	0
T1	24165	2	0	0
T2	11125	1	0	0
T3	81045	17	0	0
T4	23548	2	0	0
T5	7140	1	0	0
T6	19461	3	0	0
T7	116991	27	0	0
T8	117024	27	0	0
T9	46965	1	0	0
T10	23357	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054916	8986	0	0
T1	12079	2	0	0
T2	5561	1	0	0
T3	40518	17	0	0
T4	11779	2	0	0
T5	3569	1	0	0
T6	9726	3	0	0
T7	58497	27	0	0
T8	58521	27	0	0
T9	23483	1	0	0
T10	11678	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054916	8986	0	0
T1	12079	2	0	0
T2	5561	1	0	0
T3	40518	17	0	0
T4	11779	2	0	0
T5	3569	1	0	0
T6	9726	3	0	0
T7	58497	27	0	0
T8	58521	27	0	0
T9	23483	1	0	0
T10	11678	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	8986	0	0
T1	6039	2	0	0
T2	2780	1	0	0
T3	20262	17	0	0
T4	5887	2	0	0
T5	1784	1	0	0
T6	4864	3	0	0
T7	29251	27	0	0
T8	29258	27	0	0
T9	11741	1	0	0
T10	5840	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	8986	0	0
T1	6039	2	0	0
T2	2780	1	0	0
T3	20262	17	0	0
T4	5887	2	0	0
T5	1784	1	0	0
T6	4864	3	0	0
T7	29251	27	0	0
T8	29258	27	0	0
T9	11741	1	0	0
T10	5840	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27055421	8986	0	0
T1	12080	2	0	0
T2	5562	1	0	0
T3	40526	17	0	0
T4	11775	2	0	0
T5	3569	1	0	0
T6	9732	3	0	0
T7	58507	27	0	0
T8	58515	27	0	0
T9	23483	1	0	0
T10	11685	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27055421	8986	0	0
T1	12080	2	0	0
T2	5562	1	0	0
T3	40526	17	0	0
T4	11775	2	0	0
T5	3569	1	0	0
T6	9732	3	0	0
T7	58507	27	0	0
T8	58515	27	0	0
T9	23483	1	0	0
T10	11685	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	22404	0	0
T1	25169	6	0	0
T2	11589	5	0	0
T3	84432	56	0	0
T4	24533	6	0	0
T5	7437	1	0	0
T6	20270	7	0	0
T7	121862	102	0	0
T8	121894	102	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	22404	0	0
T1	25169	6	0	0
T2	11589	5	0	0
T3	84432	56	0	0
T4	24533	6	0	0
T5	7437	1	0	0
T6	20270	7	0	0
T7	121862	102	0	0
T8	121894	102	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	22404	0	0
T1	754	6	0	0
T2	347	5	0	0
T3	2605	56	0	0
T4	734	6	0	0
T5	222	1	0	0
T6	607	7	0	0
T7	3670	102	0	0
T8	3671	102	0	0
T9	1465	1	0	0
T10	732	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	22404	0	0
T1	754	6	0	0
T2	347	5	0	0
T3	2605	56	0	0
T4	734	6	0	0
T5	222	1	0	0
T6	607	7	0	0
T7	3670	102	0	0
T8	3671	102	0	0
T9	1465	1	0	0
T10	732	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	22404	0	0
T1	25169	6	0	0
T2	11589	5	0	0
T3	84432	56	0	0
T4	24533	6	0	0
T5	7437	1	0	0
T6	20270	7	0	0
T7	121862	102	0	0
T8	121894	102	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	22404	0	0
T1	25169	6	0	0
T2	11589	5	0	0
T3	84432	56	0	0
T4	24533	6	0	0
T5	7437	1	0	0
T6	20270	7	0	0
T7	121862	102	0	0
T8	121894	102	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	7112	0	0
T1	754	1	0	0
T2	347	1	0	0
T3	2605	8	0	0
T4	734	1	0	0
T5	222	1	0	0
T6	607	2	0	0
T7	3670	27	0	0
T8	3671	27	0	0
T9	1465	1	0	0
T10	732	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	22404	0	0
T1	25169	6	0	0
T2	11589	5	0	0
T3	84432	56	0	0
T4	24533	6	0	0
T5	7437	1	0	0
T6	20270	7	0	0
T7	121862	102	0	0
T8	121894	102	0	0
T9	48923	1	0	0
T10	24326	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56364562	22404	0	0
T1	25169	6	0	0
T2	11589	5	0	0
T3	84432	56	0	0
T4	24533	6	0	0
T5	7437	1	0	0
T6	20270	7	0	0
T7	121862	102	0	0
T8	121894	102	0	0
T9	48923	1	0	0
T10	24326	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	205	0	0
T3	2605	2	0	0
T4	734	0	0	0
T5	222	0	0	0
T6	607	0	0	0
T7	3670	0	0	0
T8	3671	0	0	0
T9	1465	0	0	0
T10	732	0	0	0
T11	267	0	0	0
T12	335	0	0	0
T13	0	2	0	0
T71	0	4	0	0
T93	0	3	0	0
T99	0	2	0	0
T100	0	11	0	0
T103	0	1	0	0
T107	0	1	0	0
T109	0	3	0	0
T123	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	8986	0	0
T1	754	2	0	0
T2	347	1	0	0
T3	2605	17	0	0
T4	734	2	0	0
T5	222	1	0	0
T6	607	3	0	0
T7	3670	27	0	0
T8	3671	27	0	0
T9	1465	1	0	0
T10	732	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	22404	0	0
T1	6039	6	0	0
T2	2780	5	0	0
T3	20262	56	0	0
T4	5887	6	0	0
T5	1784	1	0	0
T6	4864	7	0	0
T7	29251	102	0	0
T8	29258	102	0	0
T9	11741	1	0	0
T10	5840	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	22404	0	0
T1	6039	6	0	0
T2	2780	5	0	0
T3	20262	56	0	0
T4	5887	6	0	0
T5	1784	1	0	0
T6	4864	7	0	0
T7	29251	102	0	0
T8	29258	102	0	0
T9	11741	1	0	0
T10	5840	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038585	22404	0	0
T1	5797	6	0	0
T2	2355	5	0	0
T3	15595	56	0	0
T4	5692	6	0	0
T5	1766	1	0	0
T6	4433	7	0	0
T7	26060	102	0	0
T8	26039	102	0	0
T9	11674	1	0	0
T10	5295	8	0	0