Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T12,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T26
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13527202	14356	0	0
gen_assertions[0].RstEnOn_A	13527202	1120	0	0
gen_assertions[0].RstNOff_A	13527202	14356	0	0
gen_assertions[0].RstNOn_A	13527202	1120	0	0
gen_assertions[1].RstEnOff_A	54108366	13041	0	0
gen_assertions[1].RstEnOn_A	54108366	1056	0	0
gen_assertions[1].RstNOff_A	54108366	13041	0	0
gen_assertions[1].RstNOn_A	54108366	1056	0	0
gen_assertions[2].RstEnOff_A	27054916	13120	0	0
gen_assertions[2].RstEnOn_A	27054916	1086	0	0
gen_assertions[2].RstNOff_A	27054916	13120	0	0
gen_assertions[2].RstNOn_A	27054916	1086	0	0
gen_assertions[3].RstEnOff_A	27055421	13176	0	0
gen_assertions[3].RstEnOn_A	27055421	1141	0	0
gen_assertions[3].RstNOff_A	27055421	13176	0	0
gen_assertions[3].RstNOn_A	27055421	1141	0	0
gen_assertions[4].RstEnOff_A	1708152	22233	0	0
gen_assertions[4].RstEnOn_A	1708152	1163	0	0
gen_assertions[4].RstNOff_A	1708152	22233	0	0
gen_assertions[4].RstNOn_A	1708152	1163	0	0
gen_assertions[5].RstEnOff_A	13527202	14585	0	0
gen_assertions[5].RstEnOn_A	13527202	1214	0	0
gen_assertions[5].RstNOff_A	13527202	14585	0	0
gen_assertions[5].RstNOn_A	13527202	1214	0	0
gen_assertions[6].RstEnOff_A	13527202	14640	0	0
gen_assertions[6].RstEnOn_A	13527202	1268	0	0
gen_assertions[6].RstNOff_A	13527202	14640	0	0
gen_assertions[6].RstNOn_A	13527202	1268	0	0
gen_assertions[7].RstEnOff_A	13527202	14699	0	0
gen_assertions[7].RstEnOn_A	13527202	1327	0	0
gen_assertions[7].RstNOff_A	13527202	14699	0	0
gen_assertions[7].RstNOn_A	13527202	1327	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14356	0	0
T1	6039	5	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	4	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	6	0	0
T10	5840	0	0	0
T12	0	4	0	0
T13	0	173	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1120	0	0
T1	6039	1	0	0
T2	2780	1	0	0
T3	20262	0	0	0
T4	5887	0	0	0
T5	1784	0	0	0
T6	4864	0	0	0
T7	29251	0	0	0
T8	29258	0	0	0
T9	11741	6	0	0
T10	5840	0	0	0
T13	0	10	0	0
T25	0	2	0	0
T26	0	6	0	0
T53	0	8	0	0
T56	0	6	0	0
T94	0	1	0	0
T95	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14356	0	0
T1	6039	5	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	4	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	6	0	0
T10	5840	0	0	0
T12	0	4	0	0
T13	0	173	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1120	0	0
T1	6039	1	0	0
T2	2780	1	0	0
T3	20262	0	0	0
T4	5887	0	0	0
T5	1784	0	0	0
T6	4864	0	0	0
T7	29251	0	0	0
T8	29258	0	0	0
T9	11741	6	0	0
T10	5840	0	0	0
T13	0	10	0	0
T25	0	2	0	0
T26	0	6	0	0
T53	0	8	0	0
T56	0	6	0	0
T94	0	1	0	0
T95	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54108366	13041	0	0
T1	24165	4	0	0
T2	11125	4	0	0
T3	81045	32	0	0
T4	23548	4	0	0
T5	7140	0	0	0
T6	19461	4	0	0
T7	116991	68	0	0
T8	117024	65	0	0
T9	46965	6	0	0
T10	23357	0	0	0
T12	0	2	0	0
T13	0	166	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54108366	1056	0	0
T9	46965	6	0	0
T10	23357	0	0	0
T11	8573	0	0	0
T12	10744	0	0	0
T13	377220	12	0	0
T23	9814	0	0	0
T24	14330	0	0	0
T25	26134	0	0	0
T26	45848	5	0	0
T27	10798	0	0	0
T47	0	6	0	0
T53	0	3	0	0
T56	0	6	0	0
T95	0	2	0	0
T96	0	6	0	0
T97	0	6	0	0
T98	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54108366	13041	0	0
T1	24165	4	0	0
T2	11125	4	0	0
T3	81045	32	0	0
T4	23548	4	0	0
T5	7140	0	0	0
T6	19461	4	0	0
T7	116991	68	0	0
T8	117024	65	0	0
T9	46965	6	0	0
T10	23357	0	0	0
T12	0	2	0	0
T13	0	166	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54108366	1056	0	0
T9	46965	6	0	0
T10	23357	0	0	0
T11	8573	0	0	0
T12	10744	0	0	0
T13	377220	12	0	0
T23	9814	0	0	0
T24	14330	0	0	0
T25	26134	0	0	0
T26	45848	5	0	0
T27	10798	0	0	0
T47	0	6	0	0
T53	0	3	0	0
T56	0	6	0	0
T95	0	2	0	0
T96	0	6	0	0
T97	0	6	0	0
T98	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054916	13120	0	0
T1	12079	4	0	0
T2	5561	4	0	0
T3	40518	32	0	0
T4	11779	4	0	0
T5	3569	0	0	0
T6	9726	4	0	0
T7	58497	68	0	0
T8	58521	65	0	0
T9	23483	9	0	0
T10	11678	0	0	0
T12	0	2	0	0
T13	0	166	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054916	1086	0	0
T9	23483	9	0	0
T10	11678	0	0	0
T11	4286	0	0	0
T12	5369	0	0	0
T13	188621	11	0	0
T23	4906	0	0	0
T24	7166	0	0	0
T25	13066	0	0	0
T26	22925	7	0	0
T27	5399	0	0	0
T47	0	6	0	0
T53	0	1	0	0
T56	0	11	0	0
T95	0	1	0	0
T96	0	9	0	0
T99	0	6	0	0
T100	0	28	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054916	13120	0	0
T1	12079	4	0	0
T2	5561	4	0	0
T3	40518	32	0	0
T4	11779	4	0	0
T5	3569	0	0	0
T6	9726	4	0	0
T7	58497	68	0	0
T8	58521	65	0	0
T9	23483	9	0	0
T10	11678	0	0	0
T12	0	2	0	0
T13	0	166	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054916	1086	0	0
T9	23483	9	0	0
T10	11678	0	0	0
T11	4286	0	0	0
T12	5369	0	0	0
T13	188621	11	0	0
T23	4906	0	0	0
T24	7166	0	0	0
T25	13066	0	0	0
T26	22925	7	0	0
T27	5399	0	0	0
T47	0	6	0	0
T53	0	1	0	0
T56	0	11	0	0
T95	0	1	0	0
T96	0	9	0	0
T99	0	6	0	0
T100	0	28	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27055421	13176	0	0
T1	12080	5	0	0
T2	5562	4	0	0
T3	40526	32	0	0
T4	11775	4	0	0
T5	3569	0	0	0
T6	9732	4	0	0
T7	58507	68	0	0
T8	58515	65	0	0
T9	23483	10	0	0
T10	11685	0	0	0
T12	0	2	0	0
T13	0	168	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27055421	1141	0	0
T1	12080	1	0	0
T2	5562	0	0	0
T3	40526	0	0	0
T4	11775	0	0	0
T5	3569	0	0	0
T6	9732	0	0	0
T7	58507	0	0	0
T8	58515	0	0	0
T9	23483	10	0	0
T10	11685	0	0	0
T13	0	14	0	0
T26	0	8	0	0
T27	0	1	0	0
T47	0	7	0	0
T56	0	11	0	0
T94	0	1	0	0
T95	0	3	0	0
T96	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27055421	13176	0	0
T1	12080	5	0	0
T2	5562	4	0	0
T3	40526	32	0	0
T4	11775	4	0	0
T5	3569	0	0	0
T6	9732	4	0	0
T7	58507	68	0	0
T8	58515	65	0	0
T9	23483	10	0	0
T10	11685	0	0	0
T12	0	2	0	0
T13	0	168	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27055421	1141	0	0
T1	12080	1	0	0
T2	5562	0	0	0
T3	40526	0	0	0
T4	11775	0	0	0
T5	3569	0	0	0
T6	9732	0	0	0
T7	58507	0	0	0
T8	58515	0	0	0
T9	23483	10	0	0
T10	11685	0	0	0
T13	0	14	0	0
T26	0	8	0	0
T27	0	1	0	0
T47	0	7	0	0
T56	0	11	0	0
T94	0	1	0	0
T95	0	3	0	0
T96	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	22233	0	0
T1	754	6	0	0
T2	347	5	0	0
T3	2605	54	0	0
T4	734	6	0	0
T5	222	1	0	0
T6	607	6	0	0
T7	3670	77	0	0
T8	3671	73	0	0
T9	1465	12	0	0
T10	732	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	1163	0	0
T9	1465	11	0	0
T10	732	0	0	0
T11	267	0	0	0
T12	335	0	0	0
T13	12168	14	0	0
T23	305	0	0	0
T24	447	0	0	0
T25	815	0	0	0
T26	1432	10	0	0
T27	336	0	0	0
T47	0	9	0	0
T56	0	12	0	0
T95	0	2	0	0
T96	0	11	0	0
T99	0	7	0	0
T101	0	1	0	0
T102	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	22233	0	0
T1	754	6	0	0
T2	347	5	0	0
T3	2605	54	0	0
T4	734	6	0	0
T5	222	1	0	0
T6	607	6	0	0
T7	3670	77	0	0
T8	3671	73	0	0
T9	1465	12	0	0
T10	732	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708152	1163	0	0
T9	1465	11	0	0
T10	732	0	0	0
T11	267	0	0	0
T12	335	0	0	0
T13	12168	14	0	0
T23	305	0	0	0
T24	447	0	0	0
T25	815	0	0	0
T26	1432	10	0	0
T27	336	0	0	0
T47	0	9	0	0
T56	0	12	0	0
T95	0	2	0	0
T96	0	11	0	0
T99	0	7	0	0
T101	0	1	0	0
T102	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14585	0	0
T1	6039	4	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	4	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	10	0	0
T10	5840	0	0	0
T12	0	5	0	0
T13	0	173	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1214	0	0
T9	11741	10	0	0
T10	5840	0	0	0
T11	2142	0	0	0
T12	2684	1	0	0
T13	94310	11	0	0
T23	2452	0	0	0
T24	3582	0	0	0
T25	6533	0	0	0
T26	11461	11	0	0
T27	2698	0	0	0
T47	0	9	0	0
T49	0	1	0	0
T56	0	13	0	0
T95	0	2	0	0
T96	0	11	0	0
T99	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14585	0	0
T1	6039	4	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	4	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	10	0	0
T10	5840	0	0	0
T12	0	5	0	0
T13	0	173	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1214	0	0
T9	11741	10	0	0
T10	5840	0	0	0
T11	2142	0	0	0
T12	2684	1	0	0
T13	94310	11	0	0
T23	2452	0	0	0
T24	3582	0	0	0
T25	6533	0	0	0
T26	11461	11	0	0
T27	2698	0	0	0
T47	0	9	0	0
T49	0	1	0	0
T56	0	13	0	0
T95	0	2	0	0
T96	0	11	0	0
T99	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14640	0	0
T1	6039	4	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	5	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	14	0	0
T10	5840	0	0	0
T12	0	4	0	0
T13	0	176	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1268	0	0
T4	5887	1	0	0
T5	1784	0	0	0
T6	4864	0	0	0
T7	29251	0	0	0
T8	29258	0	0	0
T9	11741	14	0	0
T10	5840	0	0	0
T11	2142	0	0	0
T12	2684	0	0	0
T13	94310	13	0	0
T26	0	10	0	0
T47	0	10	0	0
T49	0	1	0	0
T56	0	11	0	0
T95	0	2	0	0
T96	0	11	0	0
T101	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14640	0	0
T1	6039	4	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	5	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	14	0	0
T10	5840	0	0	0
T12	0	4	0	0
T13	0	176	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1268	0	0
T4	5887	1	0	0
T5	1784	0	0	0
T6	4864	0	0	0
T7	29251	0	0	0
T8	29258	0	0	0
T9	11741	14	0	0
T10	5840	0	0	0
T11	2142	0	0	0
T12	2684	0	0	0
T13	94310	13	0	0
T26	0	10	0	0
T47	0	10	0	0
T49	0	1	0	0
T56	0	11	0	0
T95	0	2	0	0
T96	0	11	0	0
T101	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14699	0	0
T1	6039	4	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	4	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	12	0	0
T10	5840	0	0	0
T12	0	4	0	0
T13	0	175	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1327	0	0
T9	11741	12	0	0
T10	5840	0	0	0
T11	2142	0	0	0
T12	2684	0	0	0
T13	94310	12	0	0
T23	2452	0	0	0
T24	3582	0	0	0
T25	6533	0	0	0
T26	11461	13	0	0
T27	2698	0	0	0
T47	0	10	0	0
T56	0	14	0	0
T95	0	3	0	0
T96	0	14	0	0
T99	0	6	0	0
T100	0	26	0	0
T103	0	26	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	14699	0	0
T1	6039	4	0	0
T2	2780	4	0	0
T3	20262	39	0	0
T4	5887	4	0	0
T5	1784	0	0	0
T6	4864	4	0	0
T7	29251	75	0	0
T8	29258	75	0	0
T9	11741	12	0	0
T10	5840	0	0	0
T12	0	4	0	0
T13	0	175	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13527202	1327	0	0
T9	11741	12	0	0
T10	5840	0	0	0
T11	2142	0	0	0
T12	2684	0	0	0
T13	94310	12	0	0
T23	2452	0	0	0
T24	3582	0	0	0
T25	6533	0	0	0
T26	11461	13	0	0
T27	2698	0	0	0
T47	0	10	0	0
T56	0	14	0	0
T95	0	3	0	0
T96	0	14	0	0
T99	0	6	0	0
T100	0	26	0	0
T103	0	26	0	0