Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12853277	8815	0	0
alert_regwen_rd_A	12853277	5754	0	0
cpu_regwen_rd_A	12853277	5973	0	0
sw_rst_ctrl_n_0_rd_A	12853277	11149	0	0
sw_rst_ctrl_n_1_rd_A	12853277	11356	0	0
sw_rst_ctrl_n_2_rd_A	12853277	11544	0	0
sw_rst_ctrl_n_3_rd_A	12853277	11523	0	0
sw_rst_ctrl_n_4_rd_A	12853277	11301	0	0
sw_rst_ctrl_n_5_rd_A	12853277	11468	0	0
sw_rst_ctrl_n_6_rd_A	12853277	11234	0	0
sw_rst_ctrl_n_7_rd_A	12853277	11299	0	0
sw_rst_regwen_0_rd_A	12853277	6340	0	0
sw_rst_regwen_1_rd_A	12853277	6432	0	0
sw_rst_regwen_2_rd_A	12853277	6416	0	0
sw_rst_regwen_3_rd_A	12853277	6639	0	0
sw_rst_regwen_4_rd_A	12853277	6547	0	0
sw_rst_regwen_5_rd_A	12853277	6880	0	0
sw_rst_regwen_6_rd_A	12853277	6550	0	0
sw_rst_regwen_7_rd_A	12853277	6523	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	8815	0	0
T58	4030	20	0	0
T60	4603	162	0	0
T61	4731	494	0	0
T62	10103	564	0	0
T63	15798	606	0	0
T83	7622	449	0	0
T84	3006	316	0	0
T90	4064	392	0	0
T91	2974	283	0	0
T104	4009	625	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	5754	0	0
T14	4936	0	0	0
T15	3104	0	0	0
T39	53324	0	0	0
T54	26043	0	0	0
T56	3710	0	0	0
T77	0	53	0	0
T93	37614	66	0	0
T95	76340	93	0	0
T100	0	418	0	0
T103	0	216	0	0
T105	30424	42	0	0
T116	0	16	0	0
T117	0	274	0	0
T118	0	272	0	0
T119	0	54	0	0
T120	3876	0	0	0
T121	4818	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	5973	0	0
T14	4936	0	0	0
T15	3104	0	0	0
T39	53324	0	0	0
T54	26043	0	0	0
T56	3710	0	0	0
T77	0	52	0	0
T93	37614	68	0	0
T95	76340	129	0	0
T100	0	453	0	0
T103	0	241	0	0
T105	30424	49	0	0
T116	0	36	0	0
T117	0	229	0	0
T118	0	231	0	0
T119	0	51	0	0
T120	3876	0	0	0
T121	4818	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11149	0	0
T1	5797	15	0	0
T2	2355	10	0	0
T3	15595	0	0	0
T4	5692	11	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	183	0	0
T10	5295	0	0	0
T25	0	57	0	0
T26	0	173	0	0
T93	0	73	0	0
T95	0	146	0	0
T96	0	203	0	0
T105	0	32	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11356	0	0
T1	5797	11	0	0
T2	2355	10	0	0
T3	15595	0	0	0
T4	5692	18	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	187	0	0
T10	5295	0	0	0
T25	0	42	0	0
T26	0	151	0	0
T93	0	50	0	0
T95	0	154	0	0
T96	0	191	0	0
T105	0	30	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11544	0	0
T1	5797	11	0	0
T2	2355	26	0	0
T3	15595	0	0	0
T4	5692	2	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	169	0	0
T10	5295	0	0	0
T25	0	49	0	0
T26	0	172	0	0
T93	0	72	0	0
T95	0	146	0	0
T96	0	210	0	0
T105	0	45	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11523	0	0
T1	5797	25	0	0
T2	2355	5	0	0
T3	15595	0	0	0
T4	5692	15	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	172	0	0
T10	5295	0	0	0
T25	0	62	0	0
T26	0	200	0	0
T93	0	87	0	0
T95	0	131	0	0
T96	0	217	0	0
T105	0	39	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11301	0	0
T1	5797	16	0	0
T2	2355	8	0	0
T3	15595	0	0	0
T4	5692	7	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	182	0	0
T10	5295	0	0	0
T25	0	67	0	0
T26	0	176	0	0
T93	0	88	0	0
T95	0	167	0	0
T96	0	180	0	0
T105	0	39	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11468	0	0
T1	5797	6	0	0
T2	2355	14	0	0
T3	15595	0	0	0
T4	5692	5	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	178	0	0
T10	5295	0	0	0
T25	0	55	0	0
T26	0	201	0	0
T93	0	84	0	0
T95	0	152	0	0
T96	0	195	0	0
T105	0	33	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11234	0	0
T1	5797	13	0	0
T2	2355	15	0	0
T3	15595	0	0	0
T4	5692	17	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	186	0	0
T10	5295	0	0	0
T25	0	85	0	0
T26	0	184	0	0
T93	0	64	0	0
T95	0	139	0	0
T96	0	199	0	0
T105	0	44	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	11299	0	0
T1	5797	14	0	0
T2	2355	22	0	0
T3	15595	0	0	0
T4	5692	15	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	171	0	0
T10	5295	0	0	0
T25	0	53	0	0
T26	0	184	0	0
T93	0	66	0	0
T95	0	139	0	0
T96	0	185	0	0
T105	0	45	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6340	0	0
T1	5797	11	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	4	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	37	0	0
T10	5295	0	0	0
T26	0	34	0	0
T93	0	75	0	0
T95	0	117	0	0
T96	0	14	0	0
T101	0	4	0	0
T105	0	32	0	0
T122	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6432	0	0
T1	5797	6	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	12	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	16	0	0
T10	5295	0	0	0
T26	0	18	0	0
T93	0	98	0	0
T95	0	102	0	0
T96	0	38	0	0
T100	0	462	0	0
T101	0	10	0	0
T105	0	47	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6416	0	0
T1	5797	15	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	14	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	28	0	0
T10	5295	0	0	0
T26	0	25	0	0
T93	0	61	0	0
T95	0	87	0	0
T96	0	35	0	0
T101	0	4	0	0
T105	0	34	0	0
T122	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6639	0	0
T1	5797	15	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	5	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	33	0	0
T10	5295	0	0	0
T26	0	44	0	0
T93	0	63	0	0
T95	0	133	0	0
T96	0	35	0	0
T101	0	16	0	0
T105	0	32	0	0
T122	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6547	0	0
T1	5797	1	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	9	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	29	0	0
T10	5295	0	0	0
T26	0	33	0	0
T93	0	67	0	0
T95	0	142	0	0
T96	0	29	0	0
T101	0	7	0	0
T105	0	42	0	0
T122	0	15	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6880	0	0
T1	5797	9	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	14	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	39	0	0
T10	5295	0	0	0
T26	0	33	0	0
T93	0	87	0	0
T95	0	153	0	0
T96	0	26	0	0
T101	0	7	0	0
T105	0	50	0	0
T122	0	13	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6550	0	0
T1	5797	4	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	11	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	37	0	0
T10	5295	0	0	0
T26	0	31	0	0
T93	0	80	0	0
T95	0	95	0	0
T96	0	30	0	0
T101	0	10	0	0
T105	0	28	0	0
T122	0	11	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12853277	6523	0	0
T1	5797	7	0	0
T2	2355	0	0	0
T3	15595	0	0	0
T4	5692	7	0	0
T5	1766	0	0	0
T6	4433	0	0	0
T7	26060	0	0	0
T8	26039	0	0	0
T9	11674	23	0	0
T10	5295	0	0	0
T26	0	50	0	0
T93	0	81	0	0
T95	0	145	0	0
T96	0	43	0	0
T101	0	1	0	0
T105	0	28	0	0
T122	0	7	0	0