Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	590744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

355675

1

T1

396

T2

956

T3

5952

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	503383	1			T1	539		T2	1429		T3	8955
values[0x0]	221143	1			T1	248		T2	620		T3	3598
values[0x1]	221893	1			T1	245		T2	584		T3	3593

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	495417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

451002

1

T1

482

T2

1238

T3

7558

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3144	1			T2	9		T3	58		T5	3
valid_sources[0x01]	3196	1			T2	5		T3	59		T5	1
valid_sources[0x02]	3553	1			T2	14		T3	64		T5	1
valid_sources[0x03]	3753	1			T2	11		T3	62		T10	1
valid_sources[0x04]	3541	1			T2	10		T3	70		T5	4
valid_sources[0x05]	2921	1			T2	10		T3	53		T5	1
valid_sources[0x06]	4031	1			T2	13		T3	74		T10	4
valid_sources[0x07]	3202	1			T2	11		T3	58		T5	1
valid_sources[0x08]	4035	1			T2	13		T3	70		T5	1
valid_sources[0x09]	3659	1			T2	11		T3	73		T5	3
valid_sources[0x0a]	3459	1			T2	12		T3	68		T5	2
valid_sources[0x0b]	3089	1			T2	15		T3	83		T5	1
valid_sources[0x0c]	3126	1			T2	8		T3	55		T10	1
valid_sources[0x0d]	3850	1			T2	6		T3	76		T5	2
valid_sources[0x0e]	3181	1			T2	9		T3	74		T5	1
valid_sources[0x0f]	3802	1			T2	9		T3	60		T27	11
valid_sources[0x10]	3042	1			T2	5		T3	61		T13	1
valid_sources[0x11]	3694	1			T2	13		T3	53		T5	2
valid_sources[0x12]	3449	1			T2	12		T3	70		T13	1
valid_sources[0x13]	3044	1			T2	18		T3	65		T14	6
valid_sources[0x14]	3204	1			T2	13		T3	64		T5	2
valid_sources[0x15]	2982	1			T2	7		T3	65		T5	4
valid_sources[0x16]	3007	1			T2	10		T3	69		T5	4
valid_sources[0x17]	6349	1			T2	7		T3	60		T5	1
valid_sources[0x18]	3165	1			T2	10		T3	58		T5	4
valid_sources[0x19]	3322	1			T2	14		T3	54		T5	2
valid_sources[0x1a]	3344	1			T2	9		T3	63		T5	5
valid_sources[0x1b]	3381	1			T2	11		T3	53		T5	1
valid_sources[0x1c]	4104	1			T2	7		T3	63		T10	3
valid_sources[0x1d]	3384	1			T2	5		T3	71		T10	1
valid_sources[0x1e]	3267	1			T2	14		T3	66		T5	1
valid_sources[0x1f]	3209	1			T2	15		T3	71		T5	3
valid_sources[0x20]	3106	1			T2	8		T3	54		T5	1
valid_sources[0x21]	3325	1			T2	9		T3	70		T10	1
valid_sources[0x22]	3378	1			T2	13		T3	58		T5	2
valid_sources[0x23]	3647	1			T2	9		T3	57		T5	1
valid_sources[0x24]	3087	1			T2	6		T3	70		T5	1
valid_sources[0x25]	3469	1			T2	15		T3	73		T10	1
valid_sources[0x26]	3043	1			T2	9		T3	56		T10	4
valid_sources[0x27]	3530	1			T2	11		T3	74		T10	2
valid_sources[0x28]	3271	1			T2	11		T3	53		T8	9
valid_sources[0x29]	3278	1			T2	12		T3	70		T5	2
valid_sources[0x2a]	4005	1			T2	6		T3	60		T5	2
valid_sources[0x2b]	3411	1			T2	12		T3	55		T68	11
valid_sources[0x2c]	3278	1			T2	20		T3	69		T5	2
valid_sources[0x2d]	3689	1			T2	6		T3	59		T5	1
valid_sources[0x2e]	3695	1			T2	17		T3	72		T5	2
valid_sources[0x2f]	3162	1			T2	18		T3	75		T5	2
valid_sources[0x30]	3387	1			T2	10		T3	66		T5	3
valid_sources[0x31]	4153	1			T2	11		T3	60		T5	1
valid_sources[0x32]	3390	1			T2	10		T3	53		T5	4
valid_sources[0x33]	3325	1			T2	9		T3	60		T10	3
valid_sources[0x34]	3228	1			T2	9		T3	88		T5	2
valid_sources[0x35]	2838	1			T2	11		T3	62		T8	1
valid_sources[0x36]	3336	1			T2	11		T3	69		T5	1
valid_sources[0x37]	4441	1			T2	7		T3	68		T10	2
valid_sources[0x38]	2915	1			T2	9		T3	74		T5	3
valid_sources[0x39]	3320	1			T2	8		T3	74		T5	1
valid_sources[0x3a]	3709	1			T2	15		T3	74		T10	1
valid_sources[0x3b]	3494	1			T2	14		T3	78		T10	1
valid_sources[0x3c]	2898	1			T2	15		T3	67		T10	2
valid_sources[0x3d]	3366	1			T2	9		T3	57		T10	1
valid_sources[0x3e]	4212	1			T2	9		T3	67		T5	3
valid_sources[0x3f]	5132	1			T2	10		T3	65		T10	4
valid_sources[0x40]	3619	1			T2	12		T3	60		T5	3
valid_sources[0x41]	4614	1			T2	14		T3	59		T5	4
valid_sources[0x42]	3478	1			T2	13		T3	73		T5	3
valid_sources[0x43]	3220	1			T2	4		T3	60		T5	1
valid_sources[0x44]	6584	1			T2	5		T3	51		T10	1
valid_sources[0x45]	3517	1			T2	14		T3	70		T5	3
valid_sources[0x46]	3511	1			T2	11		T3	58		T10	2
valid_sources[0x47]	6850	1			T2	11		T3	51		T12	1
valid_sources[0x48]	3415	1			T2	11		T3	63		T5	1
valid_sources[0x49]	3556	1			T2	6		T3	54		T5	1
valid_sources[0x4a]	3342	1			T2	7		T3	65		T5	1
valid_sources[0x4b]	3663	1			T2	10		T3	61		T5	1
valid_sources[0x4c]	3005	1			T2	17		T3	59		T5	3
valid_sources[0x4d]	3353	1			T2	3		T3	61		T10	1
valid_sources[0x4e]	3269	1			T2	18		T3	59		T5	2
valid_sources[0x4f]	4590	1			T2	11		T3	75		T5	3
valid_sources[0x50]	3566	1			T2	10		T3	69		T5	1
valid_sources[0x51]	3620	1			T2	14		T3	73		T5	1
valid_sources[0x52]	3445	1			T2	13		T3	63		T5	1
valid_sources[0x53]	4238	1			T2	7		T3	74		T5	4
valid_sources[0x54]	3539	1			T2	9		T3	74		T5	2
valid_sources[0x55]	3380	1			T2	11		T3	51		T5	1
valid_sources[0x56]	3437	1			T2	10		T3	63		T5	1
valid_sources[0x57]	3034	1			T2	7		T3	50		T5	3
valid_sources[0x58]	3115	1			T2	15		T3	54		T5	3
valid_sources[0x59]	6120	1			T2	16		T3	58		T10	2
valid_sources[0x5a]	3318	1			T2	3		T3	51		T5	2
valid_sources[0x5b]	3176	1			T2	10		T3	66		T5	1
valid_sources[0x5c]	3194	1			T2	9		T3	63		T5	1
valid_sources[0x5d]	3377	1			T2	1		T3	50		T5	1
valid_sources[0x5e]	2929	1			T2	11		T3	67		T10	2
valid_sources[0x5f]	3296	1			T2	9		T3	66		T5	1
valid_sources[0x60]	3760	1			T2	6		T3	53		T6	212
valid_sources[0x61]	4178	1			T2	10		T3	57		T10	1
valid_sources[0x62]	3935	1			T2	11		T3	49		T10	2
valid_sources[0x63]	3614	1			T2	14		T3	55		T5	2
valid_sources[0x64]	2844	1			T2	7		T3	54		T5	3
valid_sources[0x65]	3565	1			T2	13		T3	64		T5	1
valid_sources[0x66]	3310	1			T2	7		T3	48		T10	2
valid_sources[0x67]	6379	1			T2	4		T3	60		T5	2
valid_sources[0x68]	3518	1			T2	12		T3	59		T10	1
valid_sources[0x69]	3113	1			T2	15		T3	47		T13	1
valid_sources[0x6a]	3500	1			T2	7		T3	58		T10	2
valid_sources[0x6b]	2973	1			T2	11		T3	76		T68	2
valid_sources[0x6c]	4093	1			T2	17		T3	39		T10	4
valid_sources[0x6d]	3517	1			T2	14		T3	64		T5	5
valid_sources[0x6e]	3961	1			T2	11		T3	53		T5	1
valid_sources[0x6f]	4376	1			T2	8		T3	66		T5	2
valid_sources[0x70]	3368	1			T2	12		T3	38		T5	1
valid_sources[0x71]	3202	1			T2	6		T3	62		T5	3
valid_sources[0x72]	4427	1			T2	11		T3	69		T5	2
valid_sources[0x73]	3372	1			T2	17		T3	76		T5	2
valid_sources[0x74]	3017	1			T2	7		T3	68		T5	5
valid_sources[0x75]	2910	1			T2	11		T3	58		T5	3
valid_sources[0x76]	4467	1			T2	14		T3	71		T12	4
valid_sources[0x77]	4251	1			T1	1032		T2	7		T3	81
valid_sources[0x78]	4498	1			T2	15		T3	61		T5	3
valid_sources[0x79]	3239	1			T2	10		T3	68		T5	1
valid_sources[0x7a]	6439	1			T2	17		T3	60		T5	2
valid_sources[0x7b]	3356	1			T2	13		T3	68		T5	1
valid_sources[0x7c]	3536	1			T2	17		T3	82		T5	1
valid_sources[0x7d]	3007	1			T2	5		T3	67		T5	2
valid_sources[0x7e]	3237	1			T2	4		T3	64		T5	5
valid_sources[0x7f]	4144	1			T2	14		T3	51		T5	4
valid_sources[0x80]	3450	1			T2	11		T3	66		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

236043

1

T1

273

T2

653

T3

4150

values[0x0]

all_enables

biggest_size

77562

1

T1

75

T2

207

T3

1203

values[0x1]

all_enables

biggest_size

42070

1

T1

48

T2

96

T3

599