Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T3,T14,T27
1	0	Covered	T2,T3,T5

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52912452	8303	0	0
CascadeEffAonToRstPorAboveRise_A	52912452	8303	0	0
CascadeEffAonToRstPorIoAboveFall_A	50794158	8303	0	0
CascadeEffAonToRstPorIoAboveRise_A	50794158	8303	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25397880	8303	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25397880	8303	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12698595	8303	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12698595	8303	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25397917	8303	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25397917	8303	0	0
CascadeLcToLcAboveFall_A	52912452	20850	0	0
CascadeLcToLcAboveRise_A	52912452	20850	0	0
CascadeLcToLcAonAboveFall_A	1603310	20850	0	0
CascadeLcToLcAonAboveRise_A	1603310	20850	0	0
CascadeLcToLcShadowedAboveFall_A	52912452	20850	0	0
CascadeLcToLcShadowedAboveRise_A	52912452	20850	0	0
CascadePorToAonAboveFall_A	1603310	6660	0	0
CascadeSysToSysAboveFall_A	52912452	20850	0	0
CascadeSysToSysAboveRise_A	52912452	20850	0	0
ScanRstToAonRise_A	1603310	187	0	0
StablePorToAonRise_A	1603310	8303	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11261223	20850	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11261223	20850	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11261223	20850	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11261223	20850	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12698595	20850	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12698595	20850	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11261223	20850	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11261223	20850	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11261223	20850	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11261223	20850	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	8303	0	0
T1	13814	1	0	0
T2	81151	15	0	0
T3	526274	108	0	0
T4	24430	8	0	0
T5	24717	2	0	0
T6	11554	2	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	8303	0	0
T1	13814	1	0	0
T2	81151	15	0	0
T3	526274	108	0	0
T4	24430	8	0	0
T5	24717	2	0	0
T6	11554	2	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50794158	8303	0	0
T1	13262	1	0	0
T2	77899	15	0	0
T3	505227	108	0	0
T4	23449	8	0	0
T5	23726	2	0	0
T6	11089	2	0	0
T7	21386	2	0	0
T8	8034	1	0	0
T9	7205	1	0	0
T10	27255	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50794158	8303	0	0
T1	13262	1	0	0
T2	77899	15	0	0
T3	505227	108	0	0
T4	23449	8	0	0
T5	23726	2	0	0
T6	11089	2	0	0
T7	21386	2	0	0
T8	8034	1	0	0
T9	7205	1	0	0
T10	27255	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25397880	8303	0	0
T1	6629	1	0	0
T2	38950	15	0	0
T3	252609	108	0	0
T4	11731	8	0	0
T5	11866	2	0	0
T6	5544	2	0	0
T7	10692	2	0	0
T8	4016	1	0	0
T9	3601	1	0	0
T10	13627	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25397880	8303	0	0
T1	6629	1	0	0
T2	38950	15	0	0
T3	252609	108	0	0
T4	11731	8	0	0
T5	11866	2	0	0
T6	5544	2	0	0
T7	10692	2	0	0
T8	4016	1	0	0
T9	3601	1	0	0
T10	13627	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12698595	8303	0	0
T1	3314	1	0	0
T2	19473	15	0	0
T3	126304	108	0	0
T4	5865	8	0	0
T5	5932	2	0	0
T6	2771	2	0	0
T7	5344	2	0	0
T8	2008	1	0	0
T9	1799	1	0	0
T10	6813	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12698595	8303	0	0
T1	3314	1	0	0
T2	19473	15	0	0
T3	126304	108	0	0
T4	5865	8	0	0
T5	5932	2	0	0
T6	2771	2	0	0
T7	5344	2	0	0
T8	2008	1	0	0
T9	1799	1	0	0
T10	6813	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25397917	8303	0	0
T1	6630	1	0	0
T2	38943	15	0	0
T3	252614	108	0	0
T4	11729	8	0	0
T5	11865	2	0	0
T6	5543	2	0	0
T7	10692	2	0	0
T8	4017	1	0	0
T9	3601	1	0	0
T10	13627	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25397917	8303	0	0
T1	6630	1	0	0
T2	38943	15	0	0
T3	252614	108	0	0
T4	11729	8	0	0
T5	11865	2	0	0
T6	5543	2	0	0
T7	10692	2	0	0
T8	4017	1	0	0
T9	3601	1	0	0
T10	13627	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	20850	0	0
T1	13814	1	0	0
T2	81151	54	0	0
T3	526274	318	0	0
T4	24430	8	0	0
T5	24717	6	0	0
T6	11554	6	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	20	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	20850	0	0
T1	13814	1	0	0
T2	81151	54	0	0
T3	526274	318	0	0
T4	24430	8	0	0
T5	24717	6	0	0
T6	11554	6	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	20	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603310	20850	0	0
T1	413	1	0	0
T2	2500	54	0	0
T3	16144	318	0	0
T4	734	8	0	0
T5	741	6	0	0
T6	346	6	0	0
T7	667	2	0	0
T8	249	1	0	0
T9	225	1	0	0
T10	851	20	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603310	20850	0	0
T1	413	1	0	0
T2	2500	54	0	0
T3	16144	318	0	0
T4	734	8	0	0
T5	741	6	0	0
T6	346	6	0	0
T7	667	2	0	0
T8	249	1	0	0
T9	225	1	0	0
T10	851	20	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	20850	0	0
T1	13814	1	0	0
T2	81151	54	0	0
T3	526274	318	0	0
T4	24430	8	0	0
T5	24717	6	0	0
T6	11554	6	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	20	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	20850	0	0
T1	13814	1	0	0
T2	81151	54	0	0
T3	526274	318	0	0
T4	24430	8	0	0
T5	24717	6	0	0
T6	11554	6	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	20	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603310	6660	0	0
T1	413	1	0	0
T2	2500	7	0	0
T3	16144	56	0	0
T4	734	8	0	0
T5	741	1	0	0
T6	346	1	0	0
T7	667	21	0	0
T8	249	1	0	0
T9	225	1	0	0
T10	851	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	20850	0	0
T1	13814	1	0	0
T2	81151	54	0	0
T3	526274	318	0	0
T4	24430	8	0	0
T5	24717	6	0	0
T6	11554	6	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	20	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52912452	20850	0	0
T1	13814	1	0	0
T2	81151	54	0	0
T3	526274	318	0	0
T4	24430	8	0	0
T5	24717	6	0	0
T6	11554	6	0	0
T7	22276	2	0	0
T8	8369	1	0	0
T9	7506	1	0	0
T10	28393	20	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603310	187	0	0
T3	16144	3	0	0
T4	734	0	0	0
T5	741	0	0	0
T6	346	0	0	0
T7	667	0	0	0
T8	249	0	0	0
T9	225	0	0	0
T10	851	0	0	0
T14	0	1	0	0
T15	731	0	0	0
T25	189	0	0	0
T27	0	2	0	0
T50	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T87	0	1	0	0
T108	0	4	0	0
T115	0	2	0	0
T129	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603310	8303	0	0
T1	413	1	0	0
T2	2500	15	0	0
T3	16144	108	0	0
T4	734	8	0	0
T5	741	2	0	0
T6	346	2	0	0
T7	667	2	0	0
T8	249	1	0	0
T9	225	1	0	0
T10	851	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12698595	20850	0	0
T1	3314	1	0	0
T2	19473	54	0	0
T3	126304	318	0	0
T4	5865	8	0	0
T5	5932	6	0	0
T6	2771	6	0	0
T7	5344	2	0	0
T8	2008	1	0	0
T9	1799	1	0	0
T10	6813	20	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12698595	20850	0	0
T1	3314	1	0	0
T2	19473	54	0	0
T3	126304	318	0	0
T4	5865	8	0	0
T5	5932	6	0	0
T6	2771	6	0	0
T7	5344	2	0	0
T8	2008	1	0	0
T9	1799	1	0	0
T10	6813	20	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11261223	20850	0	0
T1	3248	1	0	0
T2	14456	54	0	0
T3	98369	318	0	0
T4	5127	8	0	0
T5	5787	6	0	0
T6	2433	6	0	0
T7	5207	2	0	0
T8	1965	1	0	0
T9	1782	1	0	0
T10	5603	20	0	0