Module Definition
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Module : rstmgr_sw_rst_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rstmgr_sw_rst_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rstmgr_sw_rst_sva_if
Line No.TotalCoveredPercent
TOTAL88100.00
ALWAYS2111100.00
ALWAYS2111100.00
ALWAYS2111100.00
ALWAYS2111100.00
ALWAYS2111100.00
ALWAYS2111100.00
ALWAYS2111100.00
ALWAYS2111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
21 8 8


Cond Coverage for Module : rstmgr_sw_rst_sva_if
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T68
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T68
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T68
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T68
10CoveredT2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10CoveredT2,T3,T4

Assert Coverage for Module : rstmgr_sw_rst_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assertions[0].RstEnOff_A 12698595 13440 0 0
gen_assertions[0].RstEnOn_A 12698595 1101 0 0
gen_assertions[0].RstNOff_A 12698595 13440 0 0
gen_assertions[0].RstNOn_A 12698595 1101 0 0
gen_assertions[1].RstEnOff_A 50794158 12251 0 0
gen_assertions[1].RstEnOn_A 50794158 1023 0 0
gen_assertions[1].RstNOff_A 50794158 12251 0 0
gen_assertions[1].RstNOn_A 50794158 1023 0 0
gen_assertions[2].RstEnOff_A 25397880 12310 0 0
gen_assertions[2].RstEnOn_A 25397880 1028 0 0
gen_assertions[2].RstNOff_A 25397880 12310 0 0
gen_assertions[2].RstNOn_A 25397880 1028 0 0
gen_assertions[3].RstEnOff_A 25397917 12350 0 0
gen_assertions[3].RstEnOn_A 25397917 1055 0 0
gen_assertions[3].RstNOff_A 25397917 12350 0 0
gen_assertions[3].RstNOn_A 25397917 1055 0 0
gen_assertions[4].RstEnOff_A 1603310 20545 0 0
gen_assertions[4].RstEnOn_A 1603310 1127 0 0
gen_assertions[4].RstNOff_A 1603310 20545 0 0
gen_assertions[4].RstNOn_A 1603310 1127 0 0
gen_assertions[5].RstEnOff_A 12698595 13660 0 0
gen_assertions[5].RstEnOn_A 12698595 1141 0 0
gen_assertions[5].RstNOff_A 12698595 13660 0 0
gen_assertions[5].RstNOn_A 12698595 1141 0 0
gen_assertions[6].RstEnOff_A 12698595 13731 0 0
gen_assertions[6].RstEnOn_A 12698595 1218 0 0
gen_assertions[6].RstNOff_A 12698595 13731 0 0
gen_assertions[6].RstNOn_A 12698595 1218 0 0
gen_assertions[7].RstEnOff_A 12698595 13770 0 0
gen_assertions[7].RstEnOn_A 12698595 1262 0 0
gen_assertions[7].RstNOff_A 12698595 13770 0 0
gen_assertions[7].RstNOn_A 12698595 1262 0 0


gen_assertions[0].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13440 0 0
T1 3314 5 0 0
T2 19473 39 0 0
T3 126304 217 0 0
T4 5865 0 0 0
T5 5932 5 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 3 0 0

gen_assertions[0].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1101 0 0
T1 3314 5 0 0
T2 19473 0 0 0
T3 126304 7 0 0
T4 5865 0 0 0
T5 5932 1 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 1 0 0
T52 0 7 0 0
T53 0 4 0 0
T54 0 9 0 0
T56 0 5 0 0
T68 0 3 0 0
T88 0 2 0 0

gen_assertions[0].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13440 0 0
T1 3314 5 0 0
T2 19473 39 0 0
T3 126304 217 0 0
T4 5865 0 0 0
T5 5932 5 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 3 0 0

gen_assertions[0].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1101 0 0
T1 3314 5 0 0
T2 19473 0 0 0
T3 126304 7 0 0
T4 5865 0 0 0
T5 5932 1 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 1 0 0
T52 0 7 0 0
T53 0 4 0 0
T54 0 9 0 0
T56 0 5 0 0
T68 0 3 0 0
T88 0 2 0 0

gen_assertions[1].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50794158 12251 0 0
T1 13262 7 0 0
T2 77899 37 0 0
T3 505227 201 0 0
T4 23449 0 0 0
T5 23726 4 0 0
T6 11089 4 0 0
T7 21386 0 0 0
T8 8034 0 0 0
T9 7205 0 0 0
T10 27255 18 0 0
T11 0 3 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 3 0 0

gen_assertions[1].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50794158 1023 0 0
T1 13262 7 0 0
T2 77899 0 0 0
T3 505227 7 0 0
T4 23449 0 0 0
T5 23726 0 0 0
T6 11089 0 0 0
T7 21386 0 0 0
T8 8034 0 0 0
T9 7205 0 0 0
T10 27255 0 0 0
T52 0 1 0 0
T53 0 6 0 0
T54 0 9 0 0
T56 0 5 0 0
T68 0 3 0 0
T88 0 2 0 0
T108 0 16 0 0
T109 0 1 0 0

gen_assertions[1].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50794158 12251 0 0
T1 13262 7 0 0
T2 77899 37 0 0
T3 505227 201 0 0
T4 23449 0 0 0
T5 23726 4 0 0
T6 11089 4 0 0
T7 21386 0 0 0
T8 8034 0 0 0
T9 7205 0 0 0
T10 27255 18 0 0
T11 0 3 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 3 0 0

gen_assertions[1].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50794158 1023 0 0
T1 13262 7 0 0
T2 77899 0 0 0
T3 505227 7 0 0
T4 23449 0 0 0
T5 23726 0 0 0
T6 11089 0 0 0
T7 21386 0 0 0
T8 8034 0 0 0
T9 7205 0 0 0
T10 27255 0 0 0
T52 0 1 0 0
T53 0 6 0 0
T54 0 9 0 0
T56 0 5 0 0
T68 0 3 0 0
T88 0 2 0 0
T108 0 16 0 0
T109 0 1 0 0

gen_assertions[2].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397880 12310 0 0
T1 6629 9 0 0
T2 38950 37 0 0
T3 252609 202 0 0
T4 11731 0 0 0
T5 11866 5 0 0
T6 5544 4 0 0
T7 10692 0 0 0
T8 4016 0 0 0
T9 3601 0 0 0
T10 13627 18 0 0
T11 0 3 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 4 0 0

gen_assertions[2].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397880 1028 0 0
T1 6629 9 0 0
T2 38950 0 0 0
T3 252609 8 0 0
T4 11731 0 0 0
T5 11866 1 0 0
T6 5544 0 0 0
T7 10692 0 0 0
T8 4016 0 0 0
T9 3601 0 0 0
T10 13627 0 0 0
T53 0 2 0 0
T54 0 8 0 0
T56 0 6 0 0
T68 0 4 0 0
T88 0 4 0 0
T108 0 13 0 0
T109 0 3 0 0

gen_assertions[2].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397880 12310 0 0
T1 6629 9 0 0
T2 38950 37 0 0
T3 252609 202 0 0
T4 11731 0 0 0
T5 11866 5 0 0
T6 5544 4 0 0
T7 10692 0 0 0
T8 4016 0 0 0
T9 3601 0 0 0
T10 13627 18 0 0
T11 0 3 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 4 0 0

gen_assertions[2].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397880 1028 0 0
T1 6629 9 0 0
T2 38950 0 0 0
T3 252609 8 0 0
T4 11731 0 0 0
T5 11866 1 0 0
T6 5544 0 0 0
T7 10692 0 0 0
T8 4016 0 0 0
T9 3601 0 0 0
T10 13627 0 0 0
T53 0 2 0 0
T54 0 8 0 0
T56 0 6 0 0
T68 0 4 0 0
T88 0 4 0 0
T108 0 13 0 0
T109 0 3 0 0

gen_assertions[3].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397917 12350 0 0
T1 6630 9 0 0
T2 38943 37 0 0
T3 252614 202 0 0
T4 11729 0 0 0
T5 11865 4 0 0
T6 5543 4 0 0
T7 10692 0 0 0
T8 4017 0 0 0
T9 3601 0 0 0
T10 13627 18 0 0
T11 0 3 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 3 0 0

gen_assertions[3].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397917 1055 0 0
T1 6630 9 0 0
T2 38943 0 0 0
T3 252614 8 0 0
T4 11729 0 0 0
T5 11865 0 0 0
T6 5543 0 0 0
T7 10692 0 0 0
T8 4017 0 0 0
T9 3601 0 0 0
T10 13627 0 0 0
T54 0 10 0 0
T56 0 7 0 0
T68 0 3 0 0
T88 0 5 0 0
T89 0 1 0 0
T108 0 14 0 0
T109 0 5 0 0
T110 0 5 0 0

gen_assertions[3].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397917 12350 0 0
T1 6630 9 0 0
T2 38943 37 0 0
T3 252614 202 0 0
T4 11729 0 0 0
T5 11865 4 0 0
T6 5543 4 0 0
T7 10692 0 0 0
T8 4017 0 0 0
T9 3601 0 0 0
T10 13627 18 0 0
T11 0 3 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 3 0 0

gen_assertions[3].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25397917 1055 0 0
T1 6630 9 0 0
T2 38943 0 0 0
T3 252614 8 0 0
T4 11729 0 0 0
T5 11865 0 0 0
T6 5543 0 0 0
T7 10692 0 0 0
T8 4017 0 0 0
T9 3601 0 0 0
T10 13627 0 0 0
T54 0 10 0 0
T56 0 7 0 0
T68 0 3 0 0
T88 0 5 0 0
T89 0 1 0 0
T108 0 14 0 0
T109 0 5 0 0
T110 0 5 0 0

gen_assertions[4].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1603310 20545 0 0
T1 413 12 0 0
T2 2500 52 0 0
T3 16144 317 0 0
T4 734 3 0 0
T5 741 7 0 0
T6 346 6 0 0
T7 667 2 0 0
T8 249 1 0 0
T9 225 1 0 0
T10 851 20 0 0

gen_assertions[4].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1603310 1127 0 0
T1 413 11 0 0
T2 2500 0 0 0
T3 16144 6 0 0
T4 734 0 0 0
T5 741 1 0 0
T6 346 0 0 0
T7 667 0 0 0
T8 249 0 0 0
T9 225 0 0 0
T10 851 0 0 0
T54 0 9 0 0
T56 0 8 0 0
T68 0 6 0 0
T88 0 5 0 0
T89 0 1 0 0
T108 0 16 0 0
T109 0 6 0 0

gen_assertions[4].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1603310 20545 0 0
T1 413 12 0 0
T2 2500 52 0 0
T3 16144 317 0 0
T4 734 3 0 0
T5 741 7 0 0
T6 346 6 0 0
T7 667 2 0 0
T8 249 1 0 0
T9 225 1 0 0
T10 851 20 0 0

gen_assertions[4].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1603310 1127 0 0
T1 413 11 0 0
T2 2500 0 0 0
T3 16144 6 0 0
T4 734 0 0 0
T5 741 1 0 0
T6 346 0 0 0
T7 667 0 0 0
T8 249 0 0 0
T9 225 0 0 0
T10 851 0 0 0
T54 0 9 0 0
T56 0 8 0 0
T68 0 6 0 0
T88 0 5 0 0
T89 0 1 0 0
T108 0 16 0 0
T109 0 6 0 0

gen_assertions[5].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13660 0 0
T1 3314 10 0 0
T2 19473 39 0 0
T3 126304 216 0 0
T4 5865 0 0 0
T5 5932 4 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 7 0 0

gen_assertions[5].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1141 0 0
T1 3314 10 0 0
T2 19473 0 0 0
T3 126304 6 0 0
T4 5865 0 0 0
T5 5932 0 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 0 0 0
T54 0 6 0 0
T56 0 8 0 0
T68 0 7 0 0
T88 0 7 0 0
T108 0 14 0 0
T109 0 7 0 0
T110 0 8 0 0
T111 0 1 0 0

gen_assertions[5].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13660 0 0
T1 3314 10 0 0
T2 19473 39 0 0
T3 126304 216 0 0
T4 5865 0 0 0
T5 5932 4 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 7 0 0

gen_assertions[5].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1141 0 0
T1 3314 10 0 0
T2 19473 0 0 0
T3 126304 6 0 0
T4 5865 0 0 0
T5 5932 0 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 0 0 0
T54 0 6 0 0
T56 0 8 0 0
T68 0 7 0 0
T88 0 7 0 0
T108 0 14 0 0
T109 0 7 0 0
T110 0 8 0 0
T111 0 1 0 0

gen_assertions[6].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13731 0 0
T1 3314 13 0 0
T2 19473 39 0 0
T3 126304 217 0 0
T4 5865 0 0 0
T5 5932 4 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 8 0 0

gen_assertions[6].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1218 0 0
T1 3314 13 0 0
T2 19473 0 0 0
T3 126304 7 0 0
T4 5865 0 0 0
T5 5932 0 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 0 0 0
T54 0 8 0 0
T56 0 10 0 0
T68 0 8 0 0
T88 0 8 0 0
T89 0 1 0 0
T108 0 19 0 0
T109 0 8 0 0
T110 0 8 0 0

gen_assertions[6].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13731 0 0
T1 3314 13 0 0
T2 19473 39 0 0
T3 126304 217 0 0
T4 5865 0 0 0
T5 5932 4 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 8 0 0

gen_assertions[6].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1218 0 0
T1 3314 13 0 0
T2 19473 0 0 0
T3 126304 7 0 0
T4 5865 0 0 0
T5 5932 0 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 0 0 0
T54 0 8 0 0
T56 0 10 0 0
T68 0 8 0 0
T88 0 8 0 0
T89 0 1 0 0
T108 0 19 0 0
T109 0 8 0 0
T110 0 8 0 0

gen_assertions[7].RstEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13770 0 0
T1 3314 14 0 0
T2 19473 39 0 0
T3 126304 215 0 0
T4 5865 0 0 0
T5 5932 5 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 9 0 0

gen_assertions[7].RstEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1262 0 0
T1 3314 14 0 0
T2 19473 0 0 0
T3 126304 5 0 0
T4 5865 0 0 0
T5 5932 1 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 0 0 0
T54 0 10 0 0
T56 0 11 0 0
T68 0 9 0 0
T88 0 9 0 0
T89 0 1 0 0
T108 0 18 0 0
T109 0 9 0 0

gen_assertions[7].RstNOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 13770 0 0
T1 3314 14 0 0
T2 19473 39 0 0
T3 126304 215 0 0
T4 5865 0 0 0
T5 5932 5 0 0
T6 2771 4 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 19 0 0
T11 0 4 0 0
T12 0 4 0 0
T13 0 4 0 0
T68 0 9 0 0

gen_assertions[7].RstNOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12698595 1262 0 0
T1 3314 14 0 0
T2 19473 0 0 0
T3 126304 5 0 0
T4 5865 0 0 0
T5 5932 1 0 0
T6 2771 0 0 0
T7 5344 0 0 0
T8 2008 0 0 0
T9 1799 0 0 0
T10 6813 0 0 0
T54 0 10 0 0
T56 0 11 0 0
T68 0 9 0 0
T88 0 9 0 0
T89 0 1 0 0
T108 0 18 0 0
T109 0 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%