Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12103481	9146	0	0
alert_regwen_rd_A	12103481	5352	0	0
cpu_regwen_rd_A	12103481	5196	0	0
sw_rst_ctrl_n_0_rd_A	12103481	11493	0	0
sw_rst_ctrl_n_1_rd_A	12103481	10932	0	0
sw_rst_ctrl_n_2_rd_A	12103481	11330	0	0
sw_rst_ctrl_n_3_rd_A	12103481	11250	0	0
sw_rst_ctrl_n_4_rd_A	12103481	11432	0	0
sw_rst_ctrl_n_5_rd_A	12103481	11452	0	0
sw_rst_ctrl_n_6_rd_A	12103481	11254	0	0
sw_rst_ctrl_n_7_rd_A	12103481	11570	0	0
sw_rst_regwen_0_rd_A	12103481	5765	0	0
sw_rst_regwen_1_rd_A	12103481	5853	0	0
sw_rst_regwen_2_rd_A	12103481	5666	0	0
sw_rst_regwen_3_rd_A	12103481	5809	0	0
sw_rst_regwen_4_rd_A	12103481	5709	0	0
sw_rst_regwen_5_rd_A	12103481	5963	0	0
sw_rst_regwen_6_rd_A	12103481	5833	0	0
sw_rst_regwen_7_rd_A	12103481	5952	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	9146	0	0
T71	18738	3	0	0
T72	20325	1	0	0
T73	3009	94	0	0
T74	3783	50	0	0
T75	11233	496	0	0
T91	2545	259	0	0
T92	2625	201	0	0
T93	9716	1	0	0
T100	9494	1	0	0
T112	2337	16	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5352	0	0
T27	38228	19	0	0
T38	0	84	0	0
T46	26204	0	0	0
T50	45775	79	0	0
T51	5095	0	0	0
T52	2166	0	0	0
T53	2690	0	0	0
T54	41219	0	0	0
T55	34962	54	0	0
T56	11041	0	0	0
T57	1714	0	0	0
T85	0	22	0	0
T108	0	321	0	0
T115	0	32	0	0
T116	0	180	0	0
T117	0	703	0	0
T128	0	636	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5196	0	0
T27	38228	35	0	0
T38	0	67	0	0
T46	26204	0	0	0
T50	45775	89	0	0
T51	5095	0	0	0
T52	2166	0	0	0
T53	2690	0	0	0
T54	41219	0	0	0
T55	34962	47	0	0
T56	11041	0	0	0
T57	1714	0	0	0
T85	0	24	0	0
T108	0	368	0	0
T115	0	27	0	0
T116	0	210	0	0
T117	0	649	0	0
T128	0	598	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11493	0	0
T5	5787	16	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	61	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	27	0	0
T50	0	65	0	0
T55	0	68	0	0
T56	0	135	0	0
T85	0	48	0	0
T108	0	474	0	0
T109	0	105	0	0
T110	0	138	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	10932	0	0
T5	5787	7	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	90	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	27	0	0
T50	0	69	0	0
T55	0	26	0	0
T56	0	170	0	0
T85	0	42	0	0
T108	0	505	0	0
T109	0	118	0	0
T110	0	133	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11330	0	0
T5	5787	5	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	75	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	29	0	0
T50	0	74	0	0
T55	0	45	0	0
T56	0	150	0	0
T85	0	31	0	0
T108	0	503	0	0
T109	0	138	0	0
T110	0	134	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11250	0	0
T5	5787	11	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	61	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	25	0	0
T50	0	82	0	0
T55	0	59	0	0
T56	0	142	0	0
T85	0	47	0	0
T108	0	516	0	0
T109	0	136	0	0
T110	0	141	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11432	0	0
T5	5787	13	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	63	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	31	0	0
T50	0	66	0	0
T55	0	61	0	0
T56	0	180	0	0
T85	0	52	0	0
T108	0	559	0	0
T109	0	133	0	0
T110	0	125	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11452	0	0
T5	5787	15	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	70	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	36	0	0
T50	0	62	0	0
T55	0	51	0	0
T56	0	191	0	0
T85	0	41	0	0
T108	0	551	0	0
T109	0	132	0	0
T110	0	139	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11254	0	0
T5	5787	18	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	80	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	35	0	0
T50	0	68	0	0
T55	0	66	0	0
T56	0	179	0	0
T85	0	31	0	0
T108	0	509	0	0
T109	0	134	0	0
T110	0	132	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	11570	0	0
T5	5787	12	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	70	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	49	0	0
T50	0	82	0	0
T55	0	60	0	0
T56	0	157	0	0
T85	0	34	0	0
T108	0	535	0	0
T109	0	142	0	0
T110	0	131	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5765	0	0
T5	5787	6	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	36	0	0
T50	0	80	0	0
T55	0	67	0	0
T56	0	38	0	0
T85	0	52	0	0
T108	0	314	0	0
T109	0	24	0	0
T110	0	33	0	0
T115	0	44	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5853	0	0
T5	5787	10	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	31	0	0
T50	0	94	0	0
T55	0	59	0	0
T56	0	42	0	0
T85	0	42	0	0
T108	0	345	0	0
T109	0	27	0	0
T110	0	30	0	0
T115	0	36	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5666	0	0
T5	5787	2	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	19	0	0
T50	0	60	0	0
T55	0	54	0	0
T56	0	39	0	0
T85	0	41	0	0
T108	0	336	0	0
T109	0	30	0	0
T110	0	33	0	0
T115	0	12	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5809	0	0
T5	5787	9	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	44	0	0
T50	0	73	0	0
T55	0	55	0	0
T56	0	27	0	0
T85	0	27	0	0
T108	0	301	0	0
T109	0	37	0	0
T110	0	39	0	0
T115	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5709	0	0
T5	5787	5	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	21	0	0
T50	0	63	0	0
T55	0	42	0	0
T56	0	30	0	0
T85	0	37	0	0
T108	0	338	0	0
T109	0	26	0	0
T110	0	28	0	0
T115	0	28	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5963	0	0
T5	5787	10	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	43	0	0
T50	0	37	0	0
T55	0	56	0	0
T56	0	26	0	0
T85	0	33	0	0
T108	0	281	0	0
T109	0	21	0	0
T110	0	38	0	0
T115	0	34	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5833	0	0
T5	5787	7	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	21	0	0
T50	0	67	0	0
T55	0	31	0	0
T56	0	25	0	0
T85	0	45	0	0
T108	0	301	0	0
T109	0	16	0	0
T110	0	36	0	0
T115	0	30	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12103481	5952	0	0
T5	5787	10	0	0
T6	2433	0	0	0
T7	5207	0	0	0
T8	1965	0	0	0
T9	1782	0	0	0
T10	5603	0	0	0
T11	3807	0	0	0
T15	5293	0	0	0
T25	1432	0	0	0
T26	1847	0	0	0
T27	0	60	0	0
T50	0	55	0	0
T55	0	78	0	0
T56	0	51	0	0
T85	0	42	0	0
T108	0	323	0	0
T109	0	34	0	0
T110	0	40	0	0
T115	0	49	0	0