Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	655531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

393231

1

T1

95

T2

1070

T3

1142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	560517	1			T1	130		T2	1500		T3	1500
values[0x0]	244318	1			T1	67		T2	852		T3	850
values[0x1]	243927	1			T1	73		T2	848		T3	850

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	549995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

498767

1

T1

120

T2

1392

T3

1445

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3767	1			T2	32		T7	1		T10	2
valid_sources[0x01]	3387	1			T7	2		T10	2		T11	3
valid_sources[0x02]	3479	1			T2	4		T7	4		T12	2
valid_sources[0x03]	5204	1			T2	30		T6	25		T7	1
valid_sources[0x04]	5017	1			T2	14		T6	17		T7	3
valid_sources[0x05]	5120	1			T2	13		T7	4		T11	8
valid_sources[0x06]	4279	1			T7	1		T11	9		T46	1
valid_sources[0x07]	3444	1			T2	1		T7	3		T12	1
valid_sources[0x08]	3401	1			T2	3		T7	5		T10	1
valid_sources[0x09]	4668	1			T2	22		T7	1		T8	4
valid_sources[0x0a]	3845	1			T2	8		T7	4		T10	2
valid_sources[0x0b]	3431	1			T6	9		T7	3		T10	1
valid_sources[0x0c]	4666	1			T7	3		T11	10		T12	2
valid_sources[0x0d]	3806	1			T2	23		T7	6		T12	1
valid_sources[0x0e]	3538	1			T7	5		T10	2		T11	11
valid_sources[0x0f]	3865	1			T7	4		T10	1		T11	3
valid_sources[0x10]	3634	1			T2	15		T7	3		T11	2
valid_sources[0x11]	4989	1			T2	27		T7	1		T10	2
valid_sources[0x12]	3700	1			T2	4		T7	9		T10	1
valid_sources[0x13]	3892	1			T2	28		T7	5		T10	1
valid_sources[0x14]	3338	1			T7	2		T10	2		T12	1
valid_sources[0x15]	3484	1			T2	7		T7	5		T10	1
valid_sources[0x16]	4054	1			T2	30		T7	3		T8	154
valid_sources[0x17]	3882	1			T2	1		T7	3		T10	1
valid_sources[0x18]	3042	1			T2	11		T7	2		T12	1
valid_sources[0x19]	3856	1			T2	8		T7	2		T11	4
valid_sources[0x1a]	3227	1			T2	12		T7	1		T12	1
valid_sources[0x1b]	3588	1			T2	22		T7	3		T12	4
valid_sources[0x1c]	3471	1			T5	2		T7	1		T11	1
valid_sources[0x1d]	3432	1			T2	7		T7	5		T12	2
valid_sources[0x1e]	3489	1			T2	5		T7	6		T10	2
valid_sources[0x1f]	3777	1			T2	1		T7	3		T11	7
valid_sources[0x20]	3755	1			T2	52		T7	3		T10	4
valid_sources[0x21]	4362	1			T2	26		T7	1		T12	2
valid_sources[0x22]	4149	1			T7	4		T10	2		T12	1
valid_sources[0x23]	4126	1			T2	2		T7	1		T12	2
valid_sources[0x24]	3877	1			T2	23		T7	2		T10	3
valid_sources[0x25]	4443	1			T7	5		T10	1		T12	1
valid_sources[0x26]	3515	1			T7	2		T10	1		T11	3
valid_sources[0x27]	3597	1			T7	1		T10	1		T12	1
valid_sources[0x28]	3748	1			T2	20		T7	5		T10	2
valid_sources[0x29]	6390	1			T2	8		T7	4		T10	1
valid_sources[0x2a]	4422	1			T2	26		T7	5		T8	13
valid_sources[0x2b]	3924	1			T2	6		T7	4		T10	2
valid_sources[0x2c]	7832	1			T2	28		T7	1		T10	2
valid_sources[0x2d]	3701	1			T2	32		T7	3		T11	5
valid_sources[0x2e]	4378	1			T7	2		T12	1		T13	12
valid_sources[0x2f]	3640	1			T2	1		T10	1		T11	7
valid_sources[0x30]	3524	1			T2	70		T7	6		T10	1
valid_sources[0x31]	3977	1			T7	3		T8	186		T13	4
valid_sources[0x32]	3773	1			T2	7		T6	5		T7	4
valid_sources[0x33]	3577	1			T2	10		T7	4		T10	1
valid_sources[0x34]	3785	1			T2	14		T7	1		T46	5
valid_sources[0x35]	3430	1			T2	19		T7	6		T10	1
valid_sources[0x36]	3407	1			T2	25		T10	1		T11	7
valid_sources[0x37]	3881	1			T2	12		T7	5		T10	2
valid_sources[0x38]	4560	1			T2	23		T6	15		T7	5
valid_sources[0x39]	4235	1			T2	14		T7	4		T10	1
valid_sources[0x3a]	4371	1			T2	17		T7	3		T12	1
valid_sources[0x3b]	6142	1			T2	2		T7	3		T10	3
valid_sources[0x3c]	6340	1			T7	3		T10	2		T12	1
valid_sources[0x3d]	5072	1			T7	3		T10	1		T13	17
valid_sources[0x3e]	3077	1			T2	4		T6	6		T7	6
valid_sources[0x3f]	4127	1			T2	1		T7	1		T12	1
valid_sources[0x40]	4735	1			T2	15		T6	5		T7	3
valid_sources[0x41]	3479	1			T2	7		T6	1		T7	4
valid_sources[0x42]	4945	1			T2	15		T7	4		T10	1
valid_sources[0x43]	3664	1			T7	1		T10	1		T12	2
valid_sources[0x44]	3823	1			T2	9		T10	1		T12	1
valid_sources[0x45]	4227	1			T2	20		T7	3		T10	1
valid_sources[0x46]	4131	1			T2	1		T8	155		T13	9
valid_sources[0x47]	3000	1			T2	1		T7	2		T11	2
valid_sources[0x48]	3840	1			T2	25		T7	8		T10	1
valid_sources[0x49]	3959	1			T2	18		T7	3		T11	19
valid_sources[0x4a]	4274	1			T2	1		T12	1		T13	10
valid_sources[0x4b]	3512	1			T2	18		T7	1		T10	3
valid_sources[0x4c]	3961	1			T7	3		T12	1		T13	10
valid_sources[0x4d]	7609	1			T2	24		T7	4		T8	229
valid_sources[0x4e]	7334	1			T6	7		T7	3		T10	2
valid_sources[0x4f]	3516	1			T2	6		T7	4		T10	2
valid_sources[0x50]	3358	1			T2	27		T7	7		T11	11
valid_sources[0x51]	3567	1			T2	18		T7	2		T11	19
valid_sources[0x52]	7046	1			T2	13		T7	1		T10	2
valid_sources[0x53]	3801	1			T2	48		T7	3		T12	1
valid_sources[0x54]	4115	1			T2	2		T7	3		T8	150
valid_sources[0x55]	5693	1			T2	12		T7	3		T12	1
valid_sources[0x56]	3050	1			T7	4		T10	2		T12	1
valid_sources[0x57]	4450	1			T7	9		T10	1		T12	1
valid_sources[0x58]	3358	1			T2	10		T7	7		T12	5
valid_sources[0x59]	4610	1			T2	5		T7	4		T12	3
valid_sources[0x5a]	3956	1			T2	32		T5	1		T7	3
valid_sources[0x5b]	4317	1			T2	3		T6	54		T7	1
valid_sources[0x5c]	3699	1			T2	30		T7	2		T10	1
valid_sources[0x5d]	4322	1			T2	2		T7	2		T10	2
valid_sources[0x5e]	4757	1			T2	4		T8	6		T10	2
valid_sources[0x5f]	3559	1			T2	20		T6	1		T7	2
valid_sources[0x60]	3814	1			T2	9		T7	6		T10	1
valid_sources[0x61]	3755	1			T2	13		T7	3		T12	2
valid_sources[0x62]	4359	1			T2	3		T7	1		T12	6
valid_sources[0x63]	4265	1			T7	1		T10	1		T11	14
valid_sources[0x64]	4289	1			T2	45		T7	5		T10	1
valid_sources[0x65]	3805	1			T2	2		T8	140		T10	1
valid_sources[0x66]	3465	1			T7	2		T8	70		T10	1
valid_sources[0x67]	3500	1			T2	41		T6	9		T7	4
valid_sources[0x68]	5684	1			T2	59		T7	4		T11	5
valid_sources[0x69]	3668	1			T2	5		T7	7		T11	14
valid_sources[0x6a]	3966	1			T7	4		T8	533		T10	3
valid_sources[0x6b]	4896	1			T7	3		T10	2		T11	11
valid_sources[0x6c]	3580	1			T7	2		T10	1		T11	4
valid_sources[0x6d]	3841	1			T7	5		T8	1		T10	1
valid_sources[0x6e]	3552	1			T2	11		T8	12		T10	2
valid_sources[0x6f]	3609	1			T2	16		T7	2		T12	1
valid_sources[0x70]	3720	1			T7	3		T8	3		T12	2
valid_sources[0x71]	3870	1			T2	10		T7	2		T10	1
valid_sources[0x72]	3067	1			T2	44		T7	1		T12	3
valid_sources[0x73]	3820	1			T2	14		T7	7		T11	3
valid_sources[0x74]	3246	1			T2	5		T7	1		T10	1
valid_sources[0x75]	6156	1			T7	4		T10	1		T13	16
valid_sources[0x76]	3656	1			T7	3		T8	2		T10	2
valid_sources[0x77]	3473	1			T7	2		T12	1		T13	14
valid_sources[0x78]	6848	1			T7	5		T10	1		T13	9
valid_sources[0x79]	6627	1			T2	1		T7	2		T10	1
valid_sources[0x7a]	3317	1			T2	21		T7	6		T10	1
valid_sources[0x7b]	3340	1			T2	8		T7	1		T10	1
valid_sources[0x7c]	3460	1			T2	23		T7	3		T8	2
valid_sources[0x7d]	3080	1			T2	21		T7	2		T10	2
valid_sources[0x7e]	4175	1			T7	1		T10	1		T12	1
valid_sources[0x7f]	3381	1			T2	5		T7	3		T11	1
valid_sources[0x80]	3843	1			T2	4		T7	7		T8	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

261904

1

T1

70

T2

650

T3

690

values[0x0]

all_enables

biggest_size

85783

1

T1

18

T2

300

T3

303

values[0x1]

all_enables

biggest_size

45544

1

T1

7

T2

120

T3

149