Module Definition
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Module : pwrmgr_rstmgr_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.pwrmgr_rstmgr_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : pwrmgr_rstmgr_sva_if
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS3311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1


Cond Coverage for Module : pwrmgr_rstmgr_sva_if
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T8

Assert Coverage for Module : pwrmgr_rstmgr_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A 12644547 14025 0 0
gen_assertions_per_power_domains[0].LcHandshakeOn_A 12644547 129264 0 0
gen_assertions_per_power_domains[0].SysHandshakeOff_A 12644547 7920775 0 0
gen_assertions_per_power_domains[0].SysHandshakeOn_A 12644547 207257 0 0
gen_assertions_per_power_domains[1].LcHandshakeOff_A 12644547 14025 0 0
gen_assertions_per_power_domains[1].LcHandshakeOn_A 12644547 129264 0 0
gen_assertions_per_power_domains[1].SysHandshakeOff_A 12644547 7920775 0 0
gen_assertions_per_power_domains[1].SysHandshakeOn_A 12644547 207257 0 0


gen_assertions_per_power_domains[0].LcHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 14025 0 0
T1 2087 13 0 0
T2 52967 75 0 0
T3 26161 75 0 0
T4 5133 17 0 0
T5 1611 0 0 0
T6 4616 17 0 0
T7 2919 0 0 0
T8 17236 31 0 0
T9 49192 75 0 0
T10 3547 13 0 0
T12 0 4 0 0
T13 0 75 0 0

gen_assertions_per_power_domains[0].LcHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 129264 0 0
T1 2087 117 0 0
T2 52967 702 0 0
T3 26161 721 0 0
T4 5133 153 0 0
T5 1611 0 0 0
T6 4616 153 0 0
T7 2919 0 0 0
T8 17236 282 0 0
T9 49192 700 0 0
T10 3547 117 0 0
T12 0 37 0 0
T13 0 710 0 0

gen_assertions_per_power_domains[0].SysHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 7920775 0 0
T1 2087 1261 0 0
T2 52967 35790 0 0
T3 26161 8718 0 0
T4 5133 4319 0 0
T5 1611 985 0 0
T6 4616 3727 0 0
T7 2919 2278 0 0
T8 17236 7489 0 0
T9 49192 31611 0 0
T10 3547 2741 0 0

gen_assertions_per_power_domains[0].SysHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 207257 0 0
T1 2087 175 0 0
T2 52967 1141 0 0
T3 26161 1198 0 0
T4 5133 243 0 0
T5 1611 0 0 0
T6 4616 237 0 0
T7 2919 0 0 0
T8 17236 444 0 0
T9 49192 1072 0 0
T10 3547 190 0 0
T12 0 55 0 0
T13 0 1126 0 0

gen_assertions_per_power_domains[1].LcHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 14025 0 0
T1 2087 13 0 0
T2 52967 75 0 0
T3 26161 75 0 0
T4 5133 17 0 0
T5 1611 0 0 0
T6 4616 17 0 0
T7 2919 0 0 0
T8 17236 31 0 0
T9 49192 75 0 0
T10 3547 13 0 0
T12 0 4 0 0
T13 0 75 0 0

gen_assertions_per_power_domains[1].LcHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 129264 0 0
T1 2087 117 0 0
T2 52967 702 0 0
T3 26161 721 0 0
T4 5133 153 0 0
T5 1611 0 0 0
T6 4616 153 0 0
T7 2919 0 0 0
T8 17236 282 0 0
T9 49192 700 0 0
T10 3547 117 0 0
T12 0 37 0 0
T13 0 710 0 0

gen_assertions_per_power_domains[1].SysHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 7920775 0 0
T1 2087 1261 0 0
T2 52967 35790 0 0
T3 26161 8718 0 0
T4 5133 4319 0 0
T5 1611 985 0 0
T6 4616 3727 0 0
T7 2919 2278 0 0
T8 17236 7489 0 0
T9 49192 31611 0 0
T10 3547 2741 0 0

gen_assertions_per_power_domains[1].SysHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12644547 207257 0 0
T1 2087 175 0 0
T2 52967 1141 0 0
T3 26161 1198 0 0
T4 5133 243 0 0
T5 1611 0 0 0
T6 4616 237 0 0
T7 2919 0 0 0
T8 17236 444 0 0
T9 49192 1072 0 0
T10 3547 190 0 0
T12 0 55 0 0
T13 0 1126 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%