Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T25
0	1	Covered	T8,T12,T76
1	0	Covered	T8,T27,T33

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T8,T12,T25
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	59130300	8753	0	0
CascadeEffAonToRstPorAboveRise_A	59130300	8753	0	0
CascadeEffAonToRstPorIoAboveFall_A	56763206	8753	0	0
CascadeEffAonToRstPorIoAboveRise_A	56763206	8753	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	28382608	8753	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	28382608	8753	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14190970	8753	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14190970	8753	0	0
CascadeEffAonToRstPorUcbAboveFall_A	28382575	8753	0	0
CascadeEffAonToRstPorUcbAboveRise_A	28382575	8753	0	0
CascadeLcToLcAboveFall_A	59130300	22778	0	0
CascadeLcToLcAboveRise_A	59130300	22778	0	0
CascadeLcToLcAonAboveFall_A	1791872	22778	0	0
CascadeLcToLcAonAboveRise_A	1791872	22778	0	0
CascadeLcToLcShadowedAboveFall_A	59130300	22778	0	0
CascadeLcToLcShadowedAboveRise_A	59130300	22778	0	0
CascadePorToAonAboveFall_A	1791872	6808	0	0
CascadeSysToSysAboveFall_A	59130300	22778	0	0
CascadeSysToSysAboveRise_A	59130300	22778	0	0
ScanRstToAonRise_A	1791872	222	0	0
StablePorToAonRise_A	1791872	8753	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12644547	22778	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12644547	22778	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12644547	22778	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12644547	22778	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14190970	22778	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14190970	22778	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12644547	22778	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12644547	22778	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12644547	22778	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12644547	22778	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	8753	0	0
T1	12330	1	0	0
T2	235060	27	0	0
T3	122107	27	0	0
T4	26139	1	0	0
T5	6893	1	0	0
T6	24114	1	0	0
T7	12242	1	0	0
T8	90202	22	0	0
T9	216976	27	0	0
T10	18653	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	8753	0	0
T1	12330	1	0	0
T2	235060	27	0	0
T3	122107	27	0	0
T4	26139	1	0	0
T5	6893	1	0	0
T6	24114	1	0	0
T7	12242	1	0	0
T8	90202	22	0	0
T9	216976	27	0	0
T10	18653	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56763206	8753	0	0
T1	11836	1	0	0
T2	225629	27	0	0
T3	117258	27	0	0
T4	25092	1	0	0
T5	6616	1	0	0
T6	23148	1	0	0
T7	11752	1	0	0
T8	86586	22	0	0
T9	208290	27	0	0
T10	17907	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56763206	8753	0	0
T1	11836	1	0	0
T2	225629	27	0	0
T3	117258	27	0	0
T4	25092	1	0	0
T5	6616	1	0	0
T6	23148	1	0	0
T7	11752	1	0	0
T8	86586	22	0	0
T9	208290	27	0	0
T10	17907	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382608	8753	0	0
T1	5918	1	0	0
T2	112822	27	0	0
T3	58606	27	0	0
T4	12547	1	0	0
T5	3307	1	0	0
T6	11574	1	0	0
T7	5876	1	0	0
T8	43295	22	0	0
T9	104145	27	0	0
T10	8952	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382608	8753	0	0
T1	5918	1	0	0
T2	112822	27	0	0
T3	58606	27	0	0
T4	12547	1	0	0
T5	3307	1	0	0
T6	11574	1	0	0
T7	5876	1	0	0
T8	43295	22	0	0
T9	104145	27	0	0
T10	8952	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	8753	0	0
T1	2957	1	0	0
T2	56414	27	0	0
T3	29304	27	0	0
T4	6272	1	0	0
T5	1652	1	0	0
T6	5786	1	0	0
T7	2937	1	0	0
T8	21648	22	0	0
T9	52078	27	0	0
T10	4475	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	8753	0	0
T1	2957	1	0	0
T2	56414	27	0	0
T3	29304	27	0	0
T4	6272	1	0	0
T5	1652	1	0	0
T6	5786	1	0	0
T7	2937	1	0	0
T8	21648	22	0	0
T9	52078	27	0	0
T10	4475	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382575	8753	0	0
T1	5918	1	0	0
T2	112842	27	0	0
T3	58617	27	0	0
T4	12547	1	0	0
T5	3307	1	0	0
T6	11574	1	0	0
T7	5876	1	0	0
T8	43302	22	0	0
T9	104133	27	0	0
T10	8953	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382575	8753	0	0
T1	5918	1	0	0
T2	112842	27	0	0
T3	58617	27	0	0
T4	12547	1	0	0
T5	3307	1	0	0
T6	11574	1	0	0
T7	5876	1	0	0
T8	43302	22	0	0
T9	104133	27	0	0
T10	8953	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	22778	0	0
T1	12330	14	0	0
T2	235060	102	0	0
T3	122107	102	0	0
T4	26139	18	0	0
T5	6893	1	0	0
T6	24114	18	0	0
T7	12242	1	0	0
T8	90202	53	0	0
T9	216976	102	0	0
T10	18653	14	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	22778	0	0
T1	12330	14	0	0
T2	235060	102	0	0
T3	122107	102	0	0
T4	26139	18	0	0
T5	6893	1	0	0
T6	24114	18	0	0
T7	12242	1	0	0
T8	90202	53	0	0
T9	216976	102	0	0
T10	18653	14	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	22778	0	0
T1	368	14	0	0
T2	7066	102	0	0
T3	3679	102	0	0
T4	783	18	0	0
T5	205	1	0	0
T6	721	18	0	0
T7	366	1	0	0
T8	2764	53	0	0
T9	6524	102	0	0
T10	559	14	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	22778	0	0
T1	368	14	0	0
T2	7066	102	0	0
T3	3679	102	0	0
T4	783	18	0	0
T5	205	1	0	0
T6	721	18	0	0
T7	366	1	0	0
T8	2764	53	0	0
T9	6524	102	0	0
T10	559	14	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	22778	0	0
T1	12330	14	0	0
T2	235060	102	0	0
T3	122107	102	0	0
T4	26139	18	0	0
T5	6893	1	0	0
T6	24114	18	0	0
T7	12242	1	0	0
T8	90202	53	0	0
T9	216976	102	0	0
T10	18653	14	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	22778	0	0
T1	12330	14	0	0
T2	235060	102	0	0
T3	122107	102	0	0
T4	26139	18	0	0
T5	6893	1	0	0
T6	24114	18	0	0
T7	12242	1	0	0
T8	90202	53	0	0
T9	216976	102	0	0
T10	18653	14	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	6808	0	0
T1	368	1	0	0
T2	7066	27	0	0
T3	3679	27	0	0
T4	783	1	0	0
T5	205	1	0	0
T6	721	1	0	0
T7	366	1	0	0
T8	2764	10	0	0
T9	6524	27	0	0
T10	559	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	22778	0	0
T1	12330	14	0	0
T2	235060	102	0	0
T3	122107	102	0	0
T4	26139	18	0	0
T5	6893	1	0	0
T6	24114	18	0	0
T7	12242	1	0	0
T8	90202	53	0	0
T9	216976	102	0	0
T10	18653	14	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59130300	22778	0	0
T1	12330	14	0	0
T2	235060	102	0	0
T3	122107	102	0	0
T4	26139	18	0	0
T5	6893	1	0	0
T6	24114	18	0	0
T7	12242	1	0	0
T8	90202	53	0	0
T9	216976	102	0	0
T10	18653	14	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	222	0	0
T8	2764	1	0	0
T9	6524	0	0	0
T10	559	0	0	0
T11	1380	0	0	0
T12	347	1	0	0
T13	3692	0	0	0
T14	728	0	0	0
T46	212	0	0	0
T47	193	0	0	0
T77	0	3	0	0
T81	355	0	0	0
T83	0	4	0	0
T84	0	4	0	0
T86	0	4	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	5	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	8753	0	0
T1	368	1	0	0
T2	7066	27	0	0
T3	3679	27	0	0
T4	783	1	0	0
T5	205	1	0	0
T6	721	1	0	0
T7	366	1	0	0
T8	2764	22	0	0
T9	6524	27	0	0
T10	559	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	22778	0	0
T1	2957	14	0	0
T2	56414	102	0	0
T3	29304	102	0	0
T4	6272	18	0	0
T5	1652	1	0	0
T6	5786	18	0	0
T7	2937	1	0	0
T8	21648	53	0	0
T9	52078	102	0	0
T10	4475	14	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	22778	0	0
T1	2957	14	0	0
T2	56414	102	0	0
T3	29304	102	0	0
T4	6272	18	0	0
T5	1652	1	0	0
T6	5786	18	0	0
T7	2937	1	0	0
T8	21648	53	0	0
T9	52078	102	0	0
T10	4475	14	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644547	22778	0	0
T1	2087	14	0	0
T2	52967	102	0	0
T3	26161	102	0	0
T4	5133	18	0	0
T5	1611	1	0	0
T6	4616	18	0	0
T7	2919	1	0	0
T8	17236	53	0	0
T9	49192	102	0	0
T10	3547	14	0	0