Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T52
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T52
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T52
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T52
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T12
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14190970	14886	0	0
gen_assertions[0].RstEnOn_A	14190970	1048	0	0
gen_assertions[0].RstNOff_A	14190970	14886	0	0
gen_assertions[0].RstNOn_A	14190970	1048	0	0
gen_assertions[1].RstEnOff_A	56763206	13680	0	0
gen_assertions[1].RstEnOn_A	56763206	1020	0	0
gen_assertions[1].RstNOff_A	56763206	13680	0	0
gen_assertions[1].RstNOn_A	56763206	1020	0	0
gen_assertions[2].RstEnOff_A	28382608	13731	0	0
gen_assertions[2].RstEnOn_A	28382608	1000	0	0
gen_assertions[2].RstNOff_A	28382608	13731	0	0
gen_assertions[2].RstNOn_A	28382608	1000	0	0
gen_assertions[3].RstEnOff_A	28382575	13809	0	0
gen_assertions[3].RstEnOn_A	28382575	1058	0	0
gen_assertions[3].RstNOff_A	28382575	13809	0	0
gen_assertions[3].RstNOn_A	28382575	1058	0	0
gen_assertions[4].RstEnOff_A	1791872	22578	0	0
gen_assertions[4].RstEnOn_A	1791872	1082	0	0
gen_assertions[4].RstNOff_A	1791872	22578	0	0
gen_assertions[4].RstNOn_A	1791872	1082	0	0
gen_assertions[5].RstEnOff_A	14190970	15106	0	0
gen_assertions[5].RstEnOn_A	14190970	1116	0	0
gen_assertions[5].RstNOff_A	14190970	15106	0	0
gen_assertions[5].RstNOn_A	14190970	1116	0	0
gen_assertions[6].RstEnOff_A	14190970	15169	0	0
gen_assertions[6].RstEnOn_A	14190970	1175	0	0
gen_assertions[6].RstNOff_A	14190970	15169	0	0
gen_assertions[6].RstNOn_A	14190970	1175	0	0
gen_assertions[7].RstEnOff_A	14190970	15254	0	0
gen_assertions[7].RstEnOn_A	14190970	1261	0	0
gen_assertions[7].RstNOff_A	14190970	15254	0	0
gen_assertions[7].RstNOn_A	14190970	1261	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	14886	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	3	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1048	0	0
T1	2957	1	0	0
T2	56414	0	0	0
T3	29304	0	0	0
T4	6272	4	0	0
T5	1652	0	0	0
T6	5786	1	0	0
T7	2937	3	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	5	0	0
T11	0	5	0	0
T12	0	1	0	0
T28	0	6	0	0
T52	0	5	0	0
T81	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	14886	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	3	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1048	0	0
T1	2957	1	0	0
T2	56414	0	0	0
T3	29304	0	0	0
T4	6272	4	0	0
T5	1652	0	0	0
T6	5786	1	0	0
T7	2937	3	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	5	0	0
T11	0	5	0	0
T12	0	1	0	0
T28	0	6	0	0
T52	0	5	0	0
T81	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56763206	13680	0	0
T1	11836	13	0	0
T2	225629	73	0	0
T3	117258	68	0	0
T4	25092	14	0	0
T5	6616	0	0	0
T6	23148	14	0	0
T7	11752	4	0	0
T8	86586	28	0	0
T9	208290	64	0	0
T10	17907	12	0	0
T11	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56763206	1020	0	0
T1	11836	6	0	0
T2	225629	0	0	0
T3	117258	0	0	0
T4	25092	0	0	0
T5	6616	0	0	0
T6	23148	0	0	0
T7	11752	4	0	0
T8	86586	0	0	0
T9	208290	0	0	0
T10	17907	0	0	0
T11	0	3	0	0
T28	0	8	0	0
T30	0	2	0	0
T52	0	6	0	0
T77	0	8	0	0
T82	0	1	0	0
T83	0	35	0	0
T84	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56763206	13680	0	0
T1	11836	13	0	0
T2	225629	73	0	0
T3	117258	68	0	0
T4	25092	14	0	0
T5	6616	0	0	0
T6	23148	14	0	0
T7	11752	4	0	0
T8	86586	28	0	0
T9	208290	64	0	0
T10	17907	12	0	0
T11	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56763206	1020	0	0
T1	11836	6	0	0
T2	225629	0	0	0
T3	117258	0	0	0
T4	25092	0	0	0
T5	6616	0	0	0
T6	23148	0	0	0
T7	11752	4	0	0
T8	86586	0	0	0
T9	208290	0	0	0
T10	17907	0	0	0
T11	0	3	0	0
T28	0	8	0	0
T30	0	2	0	0
T52	0	6	0	0
T77	0	8	0	0
T82	0	1	0	0
T83	0	35	0	0
T84	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382608	13731	0	0
T1	5918	13	0	0
T2	112822	73	0	0
T3	58606	68	0	0
T4	12547	14	0	0
T5	3307	0	0	0
T6	11574	14	0	0
T7	5876	6	0	0
T8	43295	28	0	0
T9	104145	64	0	0
T10	8952	12	0	0
T11	0	8	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382608	1000	0	0
T7	5876	6	0	0
T8	43295	0	0	0
T9	104145	0	0	0
T10	8952	0	0	0
T11	22095	8	0	0
T12	5581	0	0	0
T13	58835	0	0	0
T14	11618	0	0	0
T27	0	1	0	0
T28	0	10	0	0
T30	0	6	0	0
T46	3430	0	0	0
T47	3096	0	0	0
T52	0	6	0	0
T77	0	7	0	0
T82	0	1	0	0
T83	0	31	0	0
T84	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382608	13731	0	0
T1	5918	13	0	0
T2	112822	73	0	0
T3	58606	68	0	0
T4	12547	14	0	0
T5	3307	0	0	0
T6	11574	14	0	0
T7	5876	6	0	0
T8	43295	28	0	0
T9	104145	64	0	0
T10	8952	12	0	0
T11	0	8	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382608	1000	0	0
T7	5876	6	0	0
T8	43295	0	0	0
T9	104145	0	0	0
T10	8952	0	0	0
T11	22095	8	0	0
T12	5581	0	0	0
T13	58835	0	0	0
T14	11618	0	0	0
T27	0	1	0	0
T28	0	10	0	0
T30	0	6	0	0
T46	3430	0	0	0
T47	3096	0	0	0
T52	0	6	0	0
T77	0	7	0	0
T82	0	1	0	0
T83	0	31	0	0
T84	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382575	13809	0	0
T1	5918	13	0	0
T2	112842	73	0	0
T3	58617	68	0	0
T4	12547	14	0	0
T5	3307	0	0	0
T6	11574	14	0	0
T7	5876	4	0	0
T8	43302	28	0	0
T9	104133	64	0	0
T10	8953	12	0	0
T11	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382575	1058	0	0
T7	5876	4	0	0
T8	43302	0	0	0
T9	104133	0	0	0
T10	8953	0	0	0
T11	22095	7	0	0
T12	5583	0	0	0
T13	58831	0	0	0
T14	11628	0	0	0
T28	0	10	0	0
T30	0	7	0	0
T46	3430	0	0	0
T47	3095	0	0	0
T52	0	6	0	0
T77	0	7	0	0
T83	0	30	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382575	13809	0	0
T1	5918	13	0	0
T2	112842	73	0	0
T3	58617	68	0	0
T4	12547	14	0	0
T5	3307	0	0	0
T6	11574	14	0	0
T7	5876	4	0	0
T8	43302	28	0	0
T9	104133	64	0	0
T10	8953	12	0	0
T11	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28382575	1058	0	0
T7	5876	4	0	0
T8	43302	0	0	0
T9	104133	0	0	0
T10	8953	0	0	0
T11	22095	7	0	0
T12	5583	0	0	0
T13	58831	0	0	0
T14	11628	0	0	0
T28	0	10	0	0
T30	0	7	0	0
T46	3430	0	0	0
T47	3095	0	0	0
T52	0	6	0	0
T77	0	7	0	0
T83	0	30	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	22578	0	0
T1	368	13	0	0
T2	7066	98	0	0
T3	3679	75	0	0
T4	783	18	0	0
T5	205	1	0	0
T6	721	18	0	0
T7	366	7	0	0
T8	2764	53	0	0
T9	6524	91	0	0
T10	559	14	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	1082	0	0
T7	366	6	0	0
T8	2764	0	0	0
T9	6524	0	0	0
T10	559	0	0	0
T11	1380	7	0	0
T12	347	0	0	0
T13	3692	0	0	0
T14	728	0	0	0
T28	0	10	0	0
T30	0	7	0	0
T46	212	0	0	0
T47	193	0	0	0
T52	0	7	0	0
T76	0	1	0	0
T77	0	7	0	0
T83	0	29	0	0
T84	0	4	0	0
T86	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	22578	0	0
T1	368	13	0	0
T2	7066	98	0	0
T3	3679	75	0	0
T4	783	18	0	0
T5	205	1	0	0
T6	721	18	0	0
T7	366	7	0	0
T8	2764	53	0	0
T9	6524	91	0	0
T10	559	14	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791872	1082	0	0
T7	366	6	0	0
T8	2764	0	0	0
T9	6524	0	0	0
T10	559	0	0	0
T11	1380	7	0	0
T12	347	0	0	0
T13	3692	0	0	0
T14	728	0	0	0
T28	0	10	0	0
T30	0	7	0	0
T46	212	0	0	0
T47	193	0	0	0
T52	0	7	0	0
T76	0	1	0	0
T77	0	7	0	0
T83	0	29	0	0
T84	0	4	0	0
T86	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	15106	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	8	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1116	0	0
T7	2937	8	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	0	0	0
T11	11046	9	0	0
T12	2791	1	0	0
T13	29416	0	0	0
T14	5811	0	0	0
T28	0	11	0	0
T30	0	8	0	0
T46	1715	0	0	0
T47	1548	0	0	0
T52	0	7	0	0
T77	0	7	0	0
T78	0	1	0	0
T82	0	1	0	0
T83	0	31	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	15106	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	8	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1116	0	0
T7	2937	8	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	0	0	0
T11	11046	9	0	0
T12	2791	1	0	0
T13	29416	0	0	0
T14	5811	0	0	0
T28	0	11	0	0
T30	0	8	0	0
T46	1715	0	0	0
T47	1548	0	0	0
T52	0	7	0	0
T77	0	7	0	0
T78	0	1	0	0
T82	0	1	0	0
T83	0	31	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	15169	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	9	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	8	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1175	0	0
T7	2937	9	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	0	0	0
T11	11046	8	0	0
T12	2791	0	0	0
T13	29416	0	0	0
T14	5811	0	0	0
T27	0	1	0	0
T28	0	12	0	0
T30	0	8	0	0
T46	1715	0	0	0
T47	1548	0	0	0
T52	0	9	0	0
T77	0	7	0	0
T78	0	1	0	0
T83	0	28	0	0
T84	0	4	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	15169	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	9	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	8	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1175	0	0
T7	2937	9	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	0	0	0
T11	11046	8	0	0
T12	2791	0	0	0
T13	29416	0	0	0
T14	5811	0	0	0
T27	0	1	0	0
T28	0	12	0	0
T30	0	8	0	0
T46	1715	0	0	0
T47	1548	0	0	0
T52	0	9	0	0
T77	0	7	0	0
T78	0	1	0	0
T83	0	28	0	0
T84	0	4	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	15254	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	10	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	12	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1261	0	0
T7	2937	10	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	0	0	0
T11	11046	12	0	0
T12	2791	1	0	0
T13	29416	0	0	0
T14	5811	0	0	0
T28	0	14	0	0
T30	0	10	0	0
T46	1715	0	0	0
T47	1548	0	0	0
T52	0	11	0	0
T77	0	9	0	0
T78	0	1	0	0
T83	0	31	0	0
T84	0	2	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	15254	0	0
T1	2957	13	0	0
T2	56414	75	0	0
T3	29304	75	0	0
T4	6272	17	0	0
T5	1652	0	0	0
T6	5786	17	0	0
T7	2937	10	0	0
T8	21648	31	0	0
T9	52078	75	0	0
T10	4475	13	0	0
T11	0	12	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14190970	1261	0	0
T7	2937	10	0	0
T8	21648	0	0	0
T9	52078	0	0	0
T10	4475	0	0	0
T11	11046	12	0	0
T12	2791	1	0	0
T13	29416	0	0	0
T14	5811	0	0	0
T28	0	14	0	0
T30	0	10	0	0
T46	1715	0	0	0
T47	1548	0	0	0
T52	0	11	0	0
T77	0	9	0	0
T78	0	1	0	0
T83	0	31	0	0
T84	0	2	0	0