Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_root_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_clean_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_out_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1339386	1307066	0	0
selKnown1	191232	158912	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1339386	1307066	0	0
T1	770	715	0	0
T2	5853	5789	0	0
T3	5853	5789	0	0
T4	999	935	0	0
T5	64	0	0	0
T6	999	935	0	0
T7	114	50	0	0
T8	3101	3037	0	0
T9	5853	5789	0	0
T10	779	715	0	0
T11	9	59	0	0
T12	0	243	0	0
T13	0	234	0	0
T14	0	414	0	0
T15	0	31	0	0
T25	0	8	0	0
T29	0	7	0	0
T33	0	1	0	0
T34	0	234	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	191232	158912	0	0
T8	832	768	0	0
T9	64	0	0	0
T10	64	0	0	0
T11	64	0	0	0
T12	128	64	0	0
T13	64	0	0	0
T14	64	0	0	0
T25	0	64	0	0
T27	0	64	0	0
T33	0	64	0	0
T46	64	0	0	0
T47	64	0	0	0
T76	0	64	0	0
T77	0	2048	0	0
T78	0	64	0	0
T79	0	960	0	0
T80	0	512	0	0
T81	64	0	0	0

Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22713	22208	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22713	22208	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	6	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22778	22273	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22778	22273	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23639	23134	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23639	23134	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	4	3	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23675	23170	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23675	23170	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	5	4	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	3	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23726	23221	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23726	23221	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	7	6	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23804	23299	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23804	23299	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	5	4	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23817	23312	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23817	23312	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	7	6	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22713	22208	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22713	22208	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	6	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23859	23354	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859	23354	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	9	8	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	23922	23417	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	23922	23417	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	10	9	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24007	23502	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24007	23502	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	11	10	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T11	0	12	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22828	22323	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22828	22323	0	0
T1	14	13	0	0
T2	102	101	0	0
T3	102	101	0	0
T4	18	17	0	0
T5	1	0	0	0
T6	18	17	0	0
T7	1	0	0	0
T8	53	52	0	0
T9	102	101	0	0
T10	14	13	0	0
T12	0	5	0	0
T14	0	8	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6794	6289	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	6794	6289	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	10	9	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	12	0	0
T29	0	7	0	0
T33	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9236	8731	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9236	8731	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	12	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T25
1	1	Covered	T8,T12,T76

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8753	8248	0	0
selKnown1	2988	2483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8753	8248	0	0
T2	27	26	0	0
T3	27	26	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	22	21	0	0
T9	27	26	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	0	1	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	1	0	0
T25	0	1	0	0
T34	0	26	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2988	2483	0	0
T8	13	12	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	2	1	0	0
T13	1	0	0	0
T14	1	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	1	0	0
T46	1	0	0	0
T47	1	0	0	0
T76	0	1	0	0
T77	0	32	0	0
T78	0	1	0	0
T79	0	15	0	0
T80	0	8	0	0
T81	1	0	0	0